xref: /gem5/src/arch/arm/isa/insts/div.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black

let {{
    sdivCode = '''
    if (Op2_sw == 0) {
        Dest_sw = 0;
    } else if (Op1_sw == INT_MIN && Op2_sw == -1) {
        Dest_sw = INT_MIN;
    } else {
        Dest_sw = Op1_sw / Op2_sw;
    }
    '''
    sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
                            { "code": sdivCode,
                              "predicate_test": predicateTest,
                              "op_class": "IntDivOp"}, [])
    header_output = RegRegRegOpDeclare.subst(sdivIop)
    decoder_output = RegRegRegOpConstructor.subst(sdivIop)
    exec_output = PredOpExecute.subst(sdivIop)

    udivCode = '''
    if (Op2_uw == 0) {
        Dest_uw = 0;
    } else {
        Dest_uw = Op1_uw / Op2_uw;
    }
    '''
    udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
                            { "code": udivCode,
                              "predicate_test": predicateTest,
                              "op_class": "IntDivOp"}, [])
    header_output += RegRegRegOpDeclare.subst(udivIop)
    decoder_output += RegRegRegOpConstructor.subst(udivIop)
    exec_output += PredOpExecute.subst(udivIop)
}};