data64.isa revision 14241
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    def createCcCode64(carry, overflow):
47        code = ""
48        code += '''
49            uint16_t _iz, _in;
50            _in = bits(resTemp, intWidth - 1);
51            _iz = ((resTemp & mask(intWidth)) == 0);
52            CondCodesNZ = (_in << 1) | _iz;
53            DPRINTF(Arm, "(in, iz) = (%d, %d)\\n", _in, _iz);
54        '''
55        if overflow and overflow != "none":
56            code +=  '''
57                uint16_t _iv;
58                _iv = %s & 1;
59                CondCodesV = _iv;
60                DPRINTF(Arm, "(iv) = (%%d)\\n", _iv);
61            ''' % overflow
62        if carry and carry != "none":
63            code += '''
64                uint16_t _ic;
65                _ic = %s & 1;
66                CondCodesC = _ic;
67                DPRINTF(Arm, "(ic) = (%%d)\\n", _ic);
68            ''' % carry
69        return code
70
71    oldC = 'CondCodesC'
72    oldV = 'CondCodesV'
73    # Dicts of ways to set the carry flag.
74    carryCode64 = {
75        "none": "none",
76        "add": 'findCarry(intWidth, resTemp, Op164, secOp)',
77        "sub": 'findCarry(intWidth, resTemp, Op164, ~secOp)',
78        "logic": '0'
79    }
80    # Dict of ways to set the overflow flag.
81    overflowCode64 = {
82        "none": "none",
83        "add": 'findOverflow(intWidth, resTemp, Op164, secOp)',
84        "sub": 'findOverflow(intWidth, resTemp, Op164, ~secOp)',
85        "logic": '0'
86    }
87
88    immOp2 = "uint64_t secOp M5_VAR_USED = imm;"
89    sRegOp2 = "uint64_t secOp M5_VAR_USED = " + \
90              "shiftReg64(Op264, shiftAmt, shiftType, intWidth);"
91    eRegOp2 = "uint64_t secOp M5_VAR_USED = " + \
92              "extendReg64(Op264, extendType, shiftAmt, intWidth);"
93
94    def buildDataWork(mnem, code, flagType, suffix, buildCc, buildNonCc,
95                      base, templateBase):
96        code = '''
97        uint64_t resTemp M5_VAR_USED = 0;
98        ''' + code
99        ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType])
100        Name = mnem.capitalize() + suffix
101        iop = InstObjParams(mnem, Name, base, code)
102        iopCc = InstObjParams(mnem + "s", Name + "Cc", base, code + ccCode)
103
104        def subst(iop):
105            global header_output, decoder_output, exec_output
106            header_output += eval(templateBase + "Declare").subst(iop)
107            decoder_output += eval(templateBase + "Constructor").subst(iop)
108            exec_output += BasicExecute.subst(iop)
109
110        if buildNonCc:
111            subst(iop)
112        if buildCc:
113            subst(iopCc)
114
115    def buildXImmDataInst(mnem, code, flagType = "logic", \
116                          buildCc = True, buildNonCc = True, \
117                          suffix = "XImm"):
118        buildDataWork(mnem, immOp2 + code, flagType, suffix,
119                      buildCc, buildNonCc, "DataXImmOp", "DataXImm")
120
121    def buildXSRegDataInst(mnem, code, flagType = "logic", \
122                           buildCc = True, buildNonCc = True, \
123                           suffix = "XSReg"):
124        buildDataWork(mnem, sRegOp2 + code, flagType, suffix,
125                      buildCc, buildNonCc, "DataXSRegOp", "DataXSReg")
126
127    def buildXERegDataInst(mnem, code, flagType = "logic", \
128                           buildCc = True, buildNonCc = True, \
129                           suffix = "XEReg"):
130        buildDataWork(mnem, eRegOp2 + code, flagType, suffix,
131                      buildCc, buildNonCc, "DataXERegOp", "DataXEReg")
132
133    def buildDataInst(mnem, code, flagType = "logic",
134                      buildCc = True, buildNonCc = True):
135        buildXImmDataInst(mnem, code, flagType, buildCc, buildNonCc)
136        buildXSRegDataInst(mnem, code, flagType, buildCc, buildNonCc)
137        buildXERegDataInst(mnem, code, flagType, buildCc, buildNonCc)
138
139    buildXImmDataInst("adr", "Dest64 = RawPC + imm", buildCc = False);
140    buildXImmDataInst("adrp", "Dest64 = (RawPC & ~mask(12)) + imm",
141                      buildCc = False);
142    buildDataInst("and", "Dest64 = resTemp = Op164 & secOp;")
143    buildDataInst("eor", "Dest64 = Op164 ^ secOp;", buildCc = False)
144    buildXSRegDataInst("eon", "Dest64 = Op164 ^ ~secOp;", buildCc = False)
145    buildDataInst("sub", "Dest64 = resTemp = Op164 - secOp;", "sub")
146    buildDataInst("add", "Dest64 = resTemp = Op164 + secOp;", "add")
147    buildXSRegDataInst("adc",
148            "Dest64 = resTemp = Op164 + secOp + %s;" % oldC, "add")
149    buildXSRegDataInst("sbc",
150            "Dest64 = resTemp = Op164 - secOp - !%s;" % oldC, "sub")
151    buildDataInst("orr", "Dest64 = Op164 | secOp;", buildCc = False)
152    buildXSRegDataInst("orn", "Dest64 = Op164 | ~secOp;", buildCc = False)
153    buildXSRegDataInst("bic", "Dest64 = resTemp = Op164 & ~secOp;")
154
155    def buildDataXImmInst(mnem, code, optArgs = []):
156        global header_output, decoder_output, exec_output
157        classNamePrefix = mnem[0].upper() + mnem[1:]
158        templateBase = "DataXImm"
159        iop = InstObjParams(mnem, classNamePrefix + "64",
160                            templateBase + "Op", code, optArgs)
161        header_output += eval(templateBase + "Declare").subst(iop)
162        decoder_output += eval(templateBase + "Constructor").subst(iop)
163        exec_output += BasicExecute.subst(iop)
164
165    def buildDataXRegInst(mnem, regOps, code, optArgs = [],
166                          overrideOpClass=None):
167        global header_output, decoder_output, exec_output
168        templateBase = "DataX%dReg" % regOps
169        classNamePrefix = mnem[0].upper() + mnem[1:]
170        if overrideOpClass:
171            iop = InstObjParams(mnem, classNamePrefix + "64",
172                                templateBase + "Op",
173                                { 'code': code, 'op_class': overrideOpClass},
174                                optArgs)
175        else:
176            iop = InstObjParams(mnem, classNamePrefix + "64",
177                                templateBase + "Op", code, optArgs)
178        header_output += eval(templateBase + "Declare").subst(iop)
179        decoder_output += eval(templateBase + "Constructor").subst(iop)
180        exec_output += BasicExecute.subst(iop)
181
182    buildDataXRegInst("madd", 3, "Dest64 = Op164 + Op264 * Op364",
183        overrideOpClass="IntMultOp")
184    buildDataXRegInst("msub", 3, "Dest64 = Op164 - Op264 * Op364",
185        overrideOpClass="IntMultOp")
186    buildDataXRegInst("smaddl", 3,
187        "XDest = XOp1 + sext<32>(WOp2) * sext<32>(WOp3)",
188        overrideOpClass="IntMultOp")
189    buildDataXRegInst("smsubl", 3,
190        "XDest = XOp1 - sext<32>(WOp2) * sext<32>(WOp3)",
191        overrideOpClass="IntMultOp")
192    buildDataXRegInst("smulh", 2, '''
193        uint64_t op1H = (int32_t)(XOp1 >> 32);
194        uint64_t op1L = (uint32_t)XOp1;
195        uint64_t op2H = (int32_t)(XOp2 >> 32);
196        uint64_t op2L = (uint32_t)XOp2;
197        uint64_t mid1 = ((op1L * op2L) >> 32) + op1H * op2L;
198        uint64_t mid2 = op1L * op2H;
199        uint64_t result = ((uint64_t)(uint32_t)mid1 + (uint32_t)mid2) >> 32;
200        result += shiftReg64(mid1, 32, ASR, intWidth);
201        result += shiftReg64(mid2, 32, ASR, intWidth);
202        XDest = result + op1H * op2H;
203    ''', overrideOpClass="IntMultOp")
204    buildDataXRegInst("umaddl", 3, "XDest = XOp1 + WOp2 * WOp3",
205        overrideOpClass="IntMultOp")
206    buildDataXRegInst("umsubl", 3, "XDest = XOp1 - WOp2 * WOp3",
207        overrideOpClass="IntMultOp")
208    buildDataXRegInst("umulh", 2, '''
209        uint64_t op1H = (uint32_t)(XOp1 >> 32);
210        uint64_t op1L = (uint32_t)XOp1;
211        uint64_t op2H = (uint32_t)(XOp2 >> 32);
212        uint64_t op2L = (uint32_t)XOp2;
213        uint64_t mid1 = ((op1L * op2L) >> 32) + op1H * op2L;
214        uint64_t mid2 = op1L * op2H;
215        uint64_t result = ((uint64_t)(uint32_t)mid1 + (uint32_t)mid2) >> 32;
216        result += mid1 >> 32;
217        result += mid2 >> 32;
218        XDest = result + op1H * op2H;
219    ''', overrideOpClass="IntMultOp")
220
221    buildDataXRegInst("asrv", 2,
222        "Dest64 = shiftReg64(Op164, Op264, ASR, intWidth)")
223    buildDataXRegInst("lslv", 2,
224        "Dest64 = shiftReg64(Op164, Op264, LSL, intWidth)")
225    buildDataXRegInst("lsrv", 2,
226        "Dest64 = shiftReg64(Op164, Op264, LSR, intWidth)")
227    buildDataXRegInst("rorv", 2,
228        "Dest64 = shiftReg64(Op164, Op264, ROR, intWidth)")
229
230    crcCode = '''
231    constexpr uint8_t size_bytes = %(sz)d;
232    constexpr uint32_t poly = %(polynom)s;
233
234    // Initial value is often a previously evaluated
235    // crc value hence is always 32bit in CRC32
236    uint32_t initial_crc = Op164 & 0xFFFFFFFF;
237
238    uint64_t data = htole(Op264);
239    auto data_buffer = reinterpret_cast<uint8_t*>(&data);
240
241    Dest = crc32<poly>(
242        data_buffer,   /* Message register */
243        initial_crc,   /* Initial value of the CRC */
244        size_bytes     /* Size of the original Message */
245    );
246    '''
247    buildDataXRegInst("crc32b", 2,
248        crcCode % {"sz": 1, "polynom": "0x04C11DB7"})
249    buildDataXRegInst("crc32h", 2,
250        crcCode % {"sz": 2, "polynom": "0x04C11DB7"})
251    buildDataXRegInst("crc32w", 2,
252        crcCode % {"sz": 4, "polynom": "0x04C11DB7"})
253    buildDataXRegInst("crc32x", 2,
254        crcCode % {"sz": 8, "polynom": "0x04C11DB7"})
255
256    buildDataXRegInst("crc32cb", 2,
257        crcCode % {"sz": 1, "polynom": "0x1EDC6F41"})
258    buildDataXRegInst("crc32ch", 2,
259        crcCode % {"sz": 2, "polynom": "0x1EDC6F41"})
260    buildDataXRegInst("crc32cw", 2,
261        crcCode % {"sz": 4, "polynom": "0x1EDC6F41"})
262    buildDataXRegInst("crc32cx", 2,
263        crcCode % {"sz": 8, "polynom": "0x1EDC6F41"})
264
265    buildDataXRegInst("sdiv", 2, '''
266        int64_t op1 = Op164;
267        int64_t op2 = Op264;
268        if (intWidth == 32) {
269            op1 = sext<32>(op1);
270            op2 = sext<32>(op2);
271        }
272        Dest64 = op2 == -1 ? -op1 : op2 ? op1 / op2 : 0;
273    ''', overrideOpClass="IntDivOp")
274    buildDataXRegInst("udiv", 2, "Dest64 = Op264 ? Op164 / Op264 : 0",
275        overrideOpClass="IntDivOp")
276
277    buildDataXRegInst("cls", 1, '''
278        uint64_t op1 = Op164;
279        if (bits(op1, intWidth - 1))
280            op1 ^= mask(intWidth);
281        Dest64 = (op1 == 0) ? intWidth - 1 : (intWidth - 2 - findMsbSet(op1));
282    ''')
283    buildDataXRegInst("clz", 1, '''
284        Dest64 = (Op164 == 0) ? intWidth : (intWidth - 1 - findMsbSet(Op164));
285    ''')
286    buildDataXRegInst("rbit", 1, '''
287        Dest64 = reverseBits(Op164, intWidth/8);
288    ''')
289    buildDataXRegInst("rev", 1, '''
290        if (intWidth == 32)
291            Dest64 = betole<uint32_t>(Op164);
292        else
293            Dest64 = betole<uint64_t>(Op164);
294    ''')
295    buildDataXRegInst("rev16", 1, '''
296        int count = intWidth / 16;
297        uint64_t result = 0;
298        for (unsigned i = 0; i < count; i++) {
299            uint16_t hw = Op164 >> (i * 16);
300            result |= (uint64_t)betole<uint16_t>(hw) << (i * 16);
301        }
302        Dest64 = result;
303    ''')
304    buildDataXRegInst("rev32", 1, '''
305        int count = intWidth / 32;
306        uint64_t result = 0;
307        for (unsigned i = 0; i < count; i++) {
308            uint32_t hw = Op164 >> (i * 32);
309            result |= (uint64_t)betole<uint32_t>(hw) << (i * 32);
310        }
311        Dest64 = result;
312    ''')
313
314    msrMrs64EnabledCheckCode = '''
315        // Check for read/write access right
316        if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) {
317            if (flat_idx == MISCREG_DAIF ||
318                flat_idx == MISCREG_DC_ZVA_Xt ||
319                flat_idx == MISCREG_DC_CVAC_Xt ||
320                flat_idx == MISCREG_DC_CIVAC_Xt
321                )
322                return std::make_shared<UndefinedInstruction>(
323                                    machInst, 0, EC_TRAPPED_MSR_MRS_64,
324                                    mnemonic);
325            return std::make_shared<UndefinedInstruction>(machInst, false,
326                                                          mnemonic);
327        }
328
329        fault = this->trap(xc->tcBase(), flat_idx, el, imm);
330        if (fault != NoFault) return fault;
331    '''
332
333    msr_check_code = '''
334        MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
335            flattenRegId(RegId(MiscRegClass, dest)).index();
336        CPSR cpsr = Cpsr;
337        ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
338        %s
339    ''' % (msrMrs64EnabledCheckCode % ('Write'),)
340
341    mrs_check_code = '''
342        MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
343            flattenRegId(RegId(MiscRegClass, op1)).index();
344        CPSR cpsr = Cpsr;
345        ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
346        %s
347    ''' % (msrMrs64EnabledCheckCode % ('Read'),)
348
349
350    mrsCode = mrs_check_code + '''
351        XDest = MiscOp1_ud;
352    '''
353    mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
354                           mrsCode,
355                           ["IsSerializeBefore"])
356    header_output += RegMiscRegOp64Declare.subst(mrsIop)
357    decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
358    exec_output += BasicExecute.subst(mrsIop)
359
360    buildDataXRegInst("mrsNZCV", 1, '''
361        CPSR cpsr = 0;
362        cpsr.nz = CondCodesNZ;
363        cpsr.c = CondCodesC;
364        cpsr.v = CondCodesV;
365        XDest = cpsr;
366    ''')
367
368    msrCode = msr_check_code + '''
369        MiscDest_ud = XOp1;
370    '''
371    msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
372                           msrCode,
373                           ["IsSerializeAfter", "IsNonSpeculative"])
374    header_output += MiscRegRegOp64Declare.subst(msrIop)
375    decoder_output += MiscRegRegOp64Constructor.subst(msrIop)
376    exec_output += BasicExecute.subst(msrIop)
377
378
379    buildDataXRegInst("msrNZCV", 1, '''
380        CPSR cpsr = XOp1;
381        CondCodesNZ = cpsr.nz;
382        CondCodesC = cpsr.c;
383        CondCodesV = cpsr.v;
384    ''')
385
386
387    msrdczva_ea_code = msr_check_code
388    msrdczva_ea_code += '''
389           Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO |
390               ArmISA::TLB::MustBeOne;
391           EA = XBase;
392           assert(!(Dczid & 0x10));
393           uint64_t op_size = power(2, Dczid + 2);
394           EA &= ~(op_size - 1);
395
396   '''
397
398    msrDCZVAIop = InstObjParams("dc zva", "Dczva", "SysDC64",
399                                { "ea_code" : msrdczva_ea_code,
400                                  "memacc_code" : ';',
401                                  "use_uops" : 0,
402                                  "op_wb" : ";",
403                                  "fa_code" : ";"},
404                                ['IsStore', 'IsMemRef']);
405    header_output += DCStore64Declare.subst(msrDCZVAIop);
406    decoder_output += DCStore64Constructor.subst(msrDCZVAIop);
407    exec_output += DCStore64Execute.subst(msrDCZVAIop);
408    exec_output += DCStore64InitiateAcc.subst(msrDCZVAIop);
409    exec_output += Store64CompleteAcc.subst(msrDCZVAIop);
410
411
412    msrdccvau_ea_code = msr_check_code
413    msrdccvau_ea_code += '''
414           Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POU |
415              ArmISA::TLB::MustBeOne;
416           EA = XBase;
417           System *sys = xc->tcBase()->getSystemPtr();
418           Addr op_size = sys->cacheLineSize();
419           EA &= ~(op_size - 1);
420    '''
421
422    msrDCCVAUIop = InstObjParams("dc cvau", "Dccvau", "SysDC64",
423                                 { "ea_code" : msrdccvau_ea_code,
424                                   "memacc_code" : ';',
425                                   "use_uops" : 0,
426                                   "op_wb" : ";", "fa_code" : ";"},
427                                 ['IsStore', 'IsMemRef']);
428    header_output += DCStore64Declare.subst(msrDCCVAUIop);
429    decoder_output += DCStore64Constructor.subst(msrDCCVAUIop);
430    exec_output += DCStore64Execute.subst(msrDCCVAUIop);
431    exec_output += DCStore64InitiateAcc.subst(msrDCCVAUIop);
432    exec_output += Store64CompleteAcc.subst(msrDCCVAUIop);
433
434
435    msrdccvac_ea_code = msr_check_code
436    msrdccvac_ea_code += '''
437           Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POC |
438              ArmISA::TLB::MustBeOne;
439           EA = XBase;
440           System *sys = xc->tcBase()->getSystemPtr();
441           Addr op_size = sys->cacheLineSize();
442           EA &= ~(op_size - 1);
443    '''
444
445    msrDCCVACIop = InstObjParams("dc cvac", "Dccvac", "SysDC64",
446                                 { "ea_code" : msrdccvac_ea_code,
447                                   "memacc_code" : ';',
448                                   "use_uops" : 0,
449                                   "op_wb" : ";", "fa_code" : ";"},
450                                 ['IsStore', 'IsMemRef']);
451    header_output += DCStore64Declare.subst(msrDCCVACIop);
452    decoder_output += DCStore64Constructor.subst(msrDCCVACIop);
453    exec_output += DCStore64Execute.subst(msrDCCVACIop);
454    exec_output += DCStore64InitiateAcc.subst(msrDCCVACIop);
455    exec_output += Store64CompleteAcc.subst(msrDCCVACIop);
456
457
458    msrdccivac_ea_code = msr_check_code
459    msrdccivac_ea_code += '''
460           Request::Flags memAccessFlags = Request::CLEAN |
461              Request::INVALIDATE | Request::DST_POC | ArmISA::TLB::MustBeOne;
462           EA = XBase;
463           System *sys = xc->tcBase()->getSystemPtr();
464           Addr op_size = sys->cacheLineSize();
465           EA &= ~(op_size - 1);
466    '''
467
468    msrDCCIVACIop = InstObjParams("dc civac", "Dccivac", "SysDC64",
469                                  { "ea_code" : msrdccivac_ea_code,
470                                    "memacc_code" : ';',
471                                    "use_uops" : 0,
472                                    "op_wb" : ";", "fa_code" : ";"},
473                                  ['IsStore', 'IsMemRef']);
474    header_output += DCStore64Declare.subst(msrDCCIVACIop);
475    decoder_output += DCStore64Constructor.subst(msrDCCIVACIop);
476    exec_output += DCStore64Execute.subst(msrDCCIVACIop);
477    exec_output += DCStore64InitiateAcc.subst(msrDCCIVACIop);
478    exec_output += Store64CompleteAcc.subst(msrDCCIVACIop);
479
480
481    msrdcivac_ea_code = msr_check_code
482    msrdcivac_ea_code += '''
483           Request::Flags memAccessFlags = Request::INVALIDATE |
484              Request::DST_POC | ArmISA::TLB::MustBeOne;
485           EA = XBase;
486           HCR hcr = Hcr64;
487           SCR scr = Scr64;
488           if (el == EL1 && ArmSystem::haveVirtualization(xc->tcBase()) &&
489               hcr.vm && (scr.ns || !ArmSystem::haveSecurity(xc->tcBase()))) {
490               memAccessFlags = memAccessFlags | Request::CLEAN;
491           }
492           System *sys = xc->tcBase()->getSystemPtr();
493           Addr op_size = sys->cacheLineSize();
494           EA &= ~(op_size - 1);
495    '''
496
497    msrDCIVACIop = InstObjParams("dc ivac", "Dcivac", "SysDC64",
498                                 { "ea_code" : msrdcivac_ea_code,
499                                   "memacc_code" : ';',
500                                   "use_uops" : 0,
501                                   "op_wb" : ";", "fa_code" : ";"},
502                                 ['IsStore', 'IsMemRef']);
503    header_output += DCStore64Declare.subst(msrDCIVACIop);
504    decoder_output += DCStore64Constructor.subst(msrDCIVACIop);
505    exec_output += DCStore64Execute.subst(msrDCIVACIop);
506    exec_output += DCStore64InitiateAcc.subst(msrDCIVACIop);
507    exec_output += Store64CompleteAcc.subst(msrDCIVACIop);
508
509    def buildMsrImmInst(mnem, inst_name, code):
510        global header_output, decoder_output, exec_output
511        msrImmPermission = '''
512            auto misc_index = (MiscRegIndex) xc->tcBase()->flattenRegId(
513               RegId(MiscRegClass, dest)).index();
514
515            if (!miscRegInfo[misc_index][MISCREG_IMPLEMENTED]) {
516                    return std::make_shared<UndefinedInstruction>(
517                                    machInst, false,
518                                    mnemonic);
519            }
520
521            if (!canWriteAArch64SysReg(misc_index,
522                Scr64, Cpsr, xc->tcBase())) {
523
524                    return std::make_shared<UndefinedInstruction>(
525                                    machInst, 0, EC_TRAPPED_MSR_MRS_64,
526                                    mnemonic);
527            }
528
529        '''
530        msrIop = InstObjParams("msr", inst_name, "MiscRegImmOp64",
531                               msrImmPermission + code,
532                               ["IsSerializeAfter", "IsNonSpeculative"])
533        header_output += MiscRegOp64Declare.subst(msrIop)
534        decoder_output += MiscRegOp64Constructor.subst(msrIop)
535        exec_output += BasicExecute.subst(msrIop)
536
537    buildMsrImmInst("msr", "MsrImm64", '''
538        // Mask and shift immediate (depending on PSTATE field)
539        // before assignment
540        MiscDest_ud = miscRegImm();
541    ''')
542
543    buildMsrImmInst("msr", "MsrImmDAIFSet64", '''
544        CPSR cpsr = Cpsr;
545        cpsr.daif = cpsr.daif | imm;
546        Cpsr = cpsr;
547    ''')
548
549    buildMsrImmInst("msr", "MsrImmDAIFClr64", '''
550        CPSR cpsr = Cpsr;
551        cpsr.daif = cpsr.daif & ~imm;
552        Cpsr = cpsr;
553    ''')
554
555    def buildDataXCompInst(mnem, instType, suffix, code):
556        global header_output, decoder_output, exec_output
557        templateBase = "DataXCond%s" % instType
558        iop = InstObjParams(mnem, mnem.capitalize() + suffix + "64",
559                            templateBase + "Op", code)
560        header_output += eval(templateBase + "Declare").subst(iop)
561        decoder_output += eval(templateBase + "Constructor").subst(iop)
562        exec_output += BasicExecute.subst(iop)
563
564    def buildDataXCondImmInst(mnem, code):
565        buildDataXCompInst(mnem, "CompImm", "Imm", code)
566    def buildDataXCondRegInst(mnem, code):
567        buildDataXCompInst(mnem, "CompReg", "Reg", code)
568    def buildDataXCondSelInst(mnem, code):
569        buildDataXCompInst(mnem, "Sel", "", code)
570
571    def condCompCode(flagType, op, imm):
572        ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType])
573        opDecl = "uint64_t secOp M5_VAR_USED = imm;"
574        if not imm:
575            opDecl = "uint64_t secOp M5_VAR_USED = Op264;"
576        return opDecl + '''
577            if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)) {
578                uint64_t resTemp = Op164 ''' + op + ''' secOp;
579        ''' + ccCode + '''
580            } else {
581                CondCodesNZ = (defCc >> 2) & 0x3;
582                CondCodesC = (defCc >> 1) & 0x1;
583                CondCodesV = defCc & 0x1;
584            }
585        '''
586
587    buildDataXCondImmInst("ccmn", condCompCode("add", "+", True))
588    buildDataXCondImmInst("ccmp", condCompCode("sub", "-", True))
589    buildDataXCondRegInst("ccmn", condCompCode("add", "+", False))
590    buildDataXCondRegInst("ccmp", condCompCode("sub", "-", False))
591
592    condSelCode = '''
593        if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)) {
594            Dest64 = Op164;
595        } else {
596            Dest64 = %(altVal)s;
597        }
598    '''
599    buildDataXCondSelInst("csel", condSelCode % {"altVal" : "Op264"})
600    buildDataXCondSelInst("csinc", condSelCode % {"altVal" : "Op264 + 1"})
601    buildDataXCondSelInst("csinv", condSelCode % {"altVal" : "~Op264"})
602    buildDataXCondSelInst("csneg", condSelCode % {"altVal" : "-Op264"})
603}};
604