data.isa revision 7858
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 calcGECode = ''' 47 CondCodes = insertBits(CondCodes, 19, 16, resTemp); 48 ''' 49 50 calcQCode = ''' 51 CondCodes = CondCodes | ((resTemp & 1) << 27); 52 ''' 53 54 calcCcCode = ''' 55 uint16_t _ic, _iv, _iz, _in; 56 _in = (resTemp >> %(negBit)d) & 1; 57 _iz = (resTemp == 0); 58 _iv = %(ivValue)s & 1; 59 _ic = %(icValue)s & 1; 60 61 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 62 (CondCodes & 0x0FFFFFFF); 63 64 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", 65 _in, _iz, _ic, _iv); 66 ''' 67 68 # Dict of code to set the carry flag. (imm, reg, reg-reg) 69 oldC = 'CondCodes<29:>' 70 oldV = 'CondCodes<28:>' 71 carryCode = { 72 "none": (oldC, oldC, oldC), 73 "llbit": (oldC, oldC, oldC), 74 "saturate": ('0', '0', '0'), 75 "overflow": ('0', '0', '0'), 76 "ge": ('0', '0', '0'), 77 "add": ('findCarry(32, resTemp, Op1, secondOp)', 78 'findCarry(32, resTemp, Op1, secondOp)', 79 'findCarry(32, resTemp, Op1, secondOp)'), 80 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)', 81 'findCarry(32, resTemp, Op1, ~secondOp)', 82 'findCarry(32, resTemp, Op1, ~secondOp)'), 83 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)', 84 'findCarry(32, resTemp, secondOp, ~Op1)', 85 'findCarry(32, resTemp, secondOp, ~Op1)'), 86 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC, 87 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC, 88 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC) 89 } 90 # Dict of code to set the overflow flag. 91 overflowCode = { 92 "none": oldV, 93 "llbit": oldV, 94 "saturate": '0', 95 "overflow": '0', 96 "ge": '0', 97 "add": 'findOverflow(32, resTemp, Op1, secondOp)', 98 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 99 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 100 "logic": oldV 101 } 102 103 secondOpRe = re.compile("secondOp") 104 immOp2 = "imm" 105 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 106 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 107 108 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ 109 buildCc = True, buildNonCc = True, instFlags = []): 110 cCode = carryCode[flagType] 111 vCode = overflowCode[flagType] 112 negBit = 31 113 if flagType == "llbit": 114 negBit = 63 115 if flagType == "saturate": 116 immCcCode = calcQCode 117 elif flagType == "ge": 118 immCcCode = calcGECode 119 else: 120 immCcCode = calcCcCode % { 121 "icValue": secondOpRe.sub(immOp2, cCode[0]), 122 "ivValue": secondOpRe.sub(immOp2, vCode), 123 "negBit": negBit 124 } 125 immCode = secondOpRe.sub(immOp2, code) 126 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", 127 {"code" : immCode, 128 "predicate_test": predicateTest}, instFlags) 129 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 130 "DataImmOp", 131 {"code" : immCode + immCcCode, 132 "predicate_test": condPredicateTest}, instFlags) 133 134 def subst(iop): 135 global header_output, decoder_output, exec_output 136 header_output += DataImmDeclare.subst(iop) 137 decoder_output += DataImmConstructor.subst(iop) 138 exec_output += PredOpExecute.subst(iop) 139 140 if buildNonCc: 141 subst(immIop) 142 if buildCc: 143 subst(immIopCc) 144 145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \ 146 buildCc = True, buildNonCc = True, instFlags = []): 147 cCode = carryCode[flagType] 148 vCode = overflowCode[flagType] 149 negBit = 31 150 if flagType == "llbit": 151 negBit = 63 152 if flagType == "saturate": 153 regCcCode = calcQCode 154 elif flagType == "ge": 155 regCcCode = calcGECode 156 else: 157 regCcCode = calcCcCode % { 158 "icValue": secondOpRe.sub(regOp2, cCode[1]), 159 "ivValue": secondOpRe.sub(regOp2, vCode), 160 "negBit": negBit 161 } 162 regCode = secondOpRe.sub(regOp2, code) 163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", 164 {"code" : regCode, 165 "predicate_test": predicateTest}, instFlags) 166 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 167 "DataRegOp", 168 {"code" : regCode + regCcCode, 169 "predicate_test": condPredicateTest}, 170 instFlags) 171 172 def subst(iop): 173 global header_output, decoder_output, exec_output 174 header_output += DataRegDeclare.subst(iop) 175 decoder_output += DataRegConstructor.subst(iop) 176 exec_output += PredOpExecute.subst(iop) 177 178 if buildNonCc: 179 subst(regIop) 180 if buildCc: 181 subst(regIopCc) 182 183 def buildRegRegDataInst(mnem, code, flagType = "logic", \ 184 suffix = "RegReg", \ 185 buildCc = True, buildNonCc = True): 186 cCode = carryCode[flagType] 187 vCode = overflowCode[flagType] 188 negBit = 31 189 if flagType == "llbit": 190 negBit = 63 191 if flagType == "saturate": 192 regRegCcCode = calcQCode 193 elif flagType == "ge": 194 regRegCcCode = calcGECode 195 else: 196 regRegCcCode = calcCcCode % { 197 "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 198 "ivValue": secondOpRe.sub(regRegOp2, vCode), 199 "negBit": negBit 200 } 201 regRegCode = secondOpRe.sub(regRegOp2, code) 202 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, 203 "DataRegRegOp", 204 {"code" : regRegCode, 205 "predicate_test": predicateTest}) 206 regRegIopCc = InstObjParams(mnem + "s", 207 mnem.capitalize() + suffix + "Cc", 208 "DataRegRegOp", 209 {"code" : regRegCode + regRegCcCode, 210 "predicate_test": condPredicateTest}) 211 212 def subst(iop): 213 global header_output, decoder_output, exec_output 214 header_output += DataRegRegDeclare.subst(iop) 215 decoder_output += DataRegRegConstructor.subst(iop) 216 exec_output += PredOpExecute.subst(iop) 217 218 if buildNonCc: 219 subst(regRegIop) 220 if buildCc: 221 subst(regRegIopCc) 222 223 def buildDataInst(mnem, code, flagType = "logic", \ 224 aiw = True, regRegAiw = True, 225 subsPcLr = True): 226 regRegCode = instCode = code 227 if aiw: 228 instCode = "AIW" + instCode 229 if regRegAiw: 230 regRegCode = "AIW" + regRegCode 231 232 buildImmDataInst(mnem, instCode, flagType) 233 buildRegDataInst(mnem, instCode, flagType) 234 buildRegRegDataInst(mnem, regRegCode, flagType) 235 if subsPcLr: 236 code += ''' 237 SCTLR sctlr = Sctlr; 238 uint32_t newCpsr = 239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 240 Cpsr = ~CondCodesMask & newCpsr; 241 CondCodes = CondCodesMask & newCpsr; 242 NextThumb = ((CPSR)newCpsr).t; 243 NextJazelle = ((CPSR)newCpsr).j; 244 ForcedItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC) 245 | (((CPSR)newCpsr).it1 & 0x3); 246 ''' 247 buildImmDataInst(mnem + 's', code, flagType, 248 suffix = "ImmPclr", buildCc = False, 249 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 250 buildRegDataInst(mnem + 's', code, flagType, 251 suffix = "RegPclr", buildCc = False, 252 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 253 254 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 255 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 256 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 257 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 258 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") 259 buildImmDataInst("adr", ''' 260 Dest = resTemp = (PC & ~0x3) + 261 (op1 ? secondOp : -secondOp); 262 ''') 263 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") 264 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub") 265 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb") 266 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False) 267 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False) 268 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False) 269 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False) 270 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;") 271 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False) 272 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False) 273 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;") 274 buildDataInst("mvn", "Dest = resTemp = ~secondOp;") 275 buildDataInst("movt", 276 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);", 277 aiw = False) 278 279 buildRegDataInst("qadd", ''' 280 int32_t midRes; 281 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw); 282 Dest = midRes; 283 ''', flagType="saturate", buildNonCc=False) 284 buildRegDataInst("qadd16", ''' 285 int32_t midRes; 286 for (unsigned i = 0; i < 2; i++) { 287 int high = (i + 1) * 16 - 1; 288 int low = i * 16; 289 int64_t arg1 = sext<16>(bits(Op1.sw, high, low)); 290 int64_t arg2 = sext<16>(bits(Op2.sw, high, low)); 291 saturateOp<16>(midRes, arg1, arg2); 292 replaceBits(resTemp, high, low, midRes); 293 } 294 Dest = resTemp; 295 ''', flagType="none", buildCc=False) 296 buildRegDataInst("qadd8", ''' 297 int32_t midRes; 298 for (unsigned i = 0; i < 4; i++) { 299 int high = (i + 1) * 8 - 1; 300 int low = i * 8; 301 int64_t arg1 = sext<8>(bits(Op1.sw, high, low)); 302 int64_t arg2 = sext<8>(bits(Op2.sw, high, low)); 303 saturateOp<8>(midRes, arg1, arg2); 304 replaceBits(resTemp, high, low, midRes); 305 } 306 Dest = resTemp; 307 ''', flagType="none", buildCc=False) 308 buildRegDataInst("qdadd", ''' 309 int32_t midRes; 310 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) | 311 saturateOp<32>(midRes, Op1.sw, midRes); 312 Dest = midRes; 313 ''', flagType="saturate", buildNonCc=False) 314 buildRegDataInst("qsub", ''' 315 int32_t midRes; 316 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true); 317 Dest = midRes; 318 ''', flagType="saturate") 319 buildRegDataInst("qsub16", ''' 320 int32_t midRes; 321 for (unsigned i = 0; i < 2; i++) { 322 int high = (i + 1) * 16 - 1; 323 int low = i * 16; 324 int64_t arg1 = sext<16>(bits(Op1.sw, high, low)); 325 int64_t arg2 = sext<16>(bits(Op2.sw, high, low)); 326 saturateOp<16>(midRes, arg1, arg2, true); 327 replaceBits(resTemp, high, low, midRes); 328 } 329 Dest = resTemp; 330 ''', flagType="none", buildCc=False) 331 buildRegDataInst("qsub8", ''' 332 int32_t midRes; 333 for (unsigned i = 0; i < 4; i++) { 334 int high = (i + 1) * 8 - 1; 335 int low = i * 8; 336 int64_t arg1 = sext<8>(bits(Op1.sw, high, low)); 337 int64_t arg2 = sext<8>(bits(Op2.sw, high, low)); 338 saturateOp<8>(midRes, arg1, arg2, true); 339 replaceBits(resTemp, high, low, midRes); 340 } 341 Dest = resTemp; 342 ''', flagType="none", buildCc=False) 343 buildRegDataInst("qdsub", ''' 344 int32_t midRes; 345 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) | 346 saturateOp<32>(midRes, Op1.sw, midRes, true); 347 Dest = midRes; 348 ''', flagType="saturate", buildNonCc=False) 349 buildRegDataInst("qasx", ''' 350 int32_t midRes; 351 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 352 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 353 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 354 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 355 saturateOp<16>(midRes, arg1Low, arg2High, true); 356 replaceBits(resTemp, 15, 0, midRes); 357 saturateOp<16>(midRes, arg1High, arg2Low); 358 replaceBits(resTemp, 31, 16, midRes); 359 Dest = resTemp; 360 ''', flagType="none", buildCc=False) 361 buildRegDataInst("qsax", ''' 362 int32_t midRes; 363 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 364 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 365 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 366 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 367 saturateOp<16>(midRes, arg1Low, arg2High); 368 replaceBits(resTemp, 15, 0, midRes); 369 saturateOp<16>(midRes, arg1High, arg2Low, true); 370 replaceBits(resTemp, 31, 16, midRes); 371 Dest = resTemp; 372 ''', flagType="none", buildCc=False) 373 374 buildRegDataInst("sadd8", ''' 375 uint32_t geBits = 0; 376 resTemp = 0; 377 for (unsigned i = 0; i < 4; i++) { 378 int high = (i + 1) * 8 - 1; 379 int low = i * 8; 380 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) + 381 sext<8>(bits(Op2.sw, high, low)); 382 replaceBits(resTemp, high, low, midRes); 383 if (midRes >= 0) { 384 geBits = geBits | (1 << i); 385 } 386 } 387 Dest = resTemp; 388 resTemp = geBits; 389 ''', flagType="ge", buildNonCc=False) 390 buildRegDataInst("sadd16", ''' 391 uint32_t geBits = 0; 392 resTemp = 0; 393 for (unsigned i = 0; i < 2; i++) { 394 int high = (i + 1) * 16 - 1; 395 int low = i * 16; 396 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) + 397 sext<16>(bits(Op2.sw, high, low)); 398 replaceBits(resTemp, high, low, midRes); 399 if (midRes >= 0) { 400 geBits = geBits | (0x3 << (i * 2)); 401 } 402 } 403 Dest = resTemp; 404 resTemp = geBits; 405 ''', flagType="ge", buildNonCc=False) 406 407 buildRegDataInst("ssub8", ''' 408 uint32_t geBits = 0; 409 resTemp = 0; 410 for (unsigned i = 0; i < 4; i++) { 411 int high = (i + 1) * 8 - 1; 412 int low = i * 8; 413 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) - 414 sext<8>(bits(Op2.sw, high, low)); 415 replaceBits(resTemp, high, low, midRes); 416 if (midRes >= 0) { 417 geBits = geBits | (1 << i); 418 } 419 } 420 Dest = resTemp; 421 resTemp = geBits; 422 ''', flagType="ge", buildNonCc=False) 423 buildRegDataInst("ssub16", ''' 424 uint32_t geBits = 0; 425 resTemp = 0; 426 for (unsigned i = 0; i < 2; i++) { 427 int high = (i + 1) * 16 - 1; 428 int low = i * 16; 429 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) - 430 sext<16>(bits(Op2.sw, high, low)); 431 replaceBits(resTemp, high, low, midRes); 432 if (midRes >= 0) { 433 geBits = geBits | (0x3 << (i * 2)); 434 } 435 } 436 Dest = resTemp; 437 resTemp = geBits; 438 ''', flagType="ge", buildNonCc=False) 439 buildRegDataInst("sasx", ''' 440 int32_t midRes, geBits = 0; 441 resTemp = 0; 442 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 443 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 444 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 445 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 446 midRes = arg1Low - arg2High; 447 if (midRes >= 0) { 448 geBits = geBits | 0x3; 449 } 450 replaceBits(resTemp, 15, 0, midRes); 451 midRes = arg1High + arg2Low; 452 if (midRes >= 0) { 453 geBits = geBits | 0xc; 454 } 455 replaceBits(resTemp, 31, 16, midRes); 456 Dest = resTemp; 457 resTemp = geBits; 458 ''', flagType="ge", buildNonCc=True) 459 buildRegDataInst("ssax", ''' 460 int32_t midRes, geBits = 0; 461 resTemp = 0; 462 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 463 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 464 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 465 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 466 midRes = arg1Low + arg2High; 467 if (midRes >= 0) { 468 geBits = geBits | 0x3; 469 } 470 replaceBits(resTemp, 15, 0, midRes); 471 midRes = arg1High - arg2Low; 472 if (midRes >= 0) { 473 geBits = geBits | 0xc; 474 } 475 replaceBits(resTemp, 31, 16, midRes); 476 Dest = resTemp; 477 resTemp = geBits; 478 ''', flagType="ge", buildNonCc=True) 479 480 buildRegDataInst("shadd8", ''' 481 resTemp = 0; 482 for (unsigned i = 0; i < 4; i++) { 483 int high = (i + 1) * 8 - 1; 484 int low = i * 8; 485 int32_t midRes = 486 (uint64_t)(sext<8>(bits(Op1.sw, high, low)) + 487 sext<8>(bits(Op2.sw, high, low))) >> 1; 488 replaceBits(resTemp, high, low, midRes); 489 } 490 Dest = resTemp; 491 ''', flagType="none", buildCc=False) 492 buildRegDataInst("shadd16", ''' 493 resTemp = 0; 494 for (unsigned i = 0; i < 2; i++) { 495 int high = (i + 1) * 16 - 1; 496 int low = i * 16; 497 int32_t midRes = 498 (uint64_t)(sext<16>(bits(Op1.sw, high, low)) + 499 sext<16>(bits(Op2.sw, high, low))) >> 1; 500 replaceBits(resTemp, high, low, midRes); 501 } 502 Dest = resTemp; 503 ''', flagType="none", buildCc=False) 504 buildRegDataInst("shsub8", ''' 505 resTemp = 0; 506 for (unsigned i = 0; i < 4; i++) { 507 int high = (i + 1) * 8 - 1; 508 int low = i * 8; 509 int32_t midRes = 510 (uint64_t)(sext<8>(bits(Op1.sw, high, low)) - 511 sext<8>(bits(Op2.sw, high, low))) >> 1; 512 replaceBits(resTemp, high, low, midRes); 513 } 514 Dest = resTemp; 515 ''', flagType="none", buildCc=False) 516 buildRegDataInst("shsub16", ''' 517 resTemp = 0; 518 for (unsigned i = 0; i < 2; i++) { 519 int high = (i + 1) * 16 - 1; 520 int low = i * 16; 521 int32_t midRes = 522 (uint64_t)(sext<16>(bits(Op1.sw, high, low)) - 523 sext<16>(bits(Op2.sw, high, low))) >> 1; 524 replaceBits(resTemp, high, low, midRes); 525 } 526 Dest = resTemp; 527 ''', flagType="none", buildCc=False) 528 buildRegDataInst("shasx", ''' 529 int32_t midRes; 530 resTemp = 0; 531 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 532 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 533 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 534 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 535 midRes = (uint64_t)(arg1Low - arg2High) >> 1; 536 replaceBits(resTemp, 15, 0, midRes); 537 midRes = (arg1High + arg2Low) >> 1; 538 replaceBits(resTemp, 31, 16, midRes); 539 Dest = resTemp; 540 ''', flagType="none", buildCc=True) 541 buildRegDataInst("shsax", ''' 542 int32_t midRes; 543 resTemp = 0; 544 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 545 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 546 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 547 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 548 midRes = (uint64_t)(arg1Low + arg2High) >> 1; 549 replaceBits(resTemp, 15, 0, midRes); 550 midRes = (uint64_t)(arg1High - arg2Low) >> 1; 551 replaceBits(resTemp, 31, 16, midRes); 552 Dest = resTemp; 553 ''', flagType="none", buildCc=True) 554 555 buildRegDataInst("uqadd16", ''' 556 uint32_t midRes; 557 for (unsigned i = 0; i < 2; i++) { 558 int high = (i + 1) * 16 - 1; 559 int low = i * 16; 560 uint64_t arg1 = bits(Op1, high, low); 561 uint64_t arg2 = bits(Op2, high, low); 562 uSaturateOp<16>(midRes, arg1, arg2); 563 replaceBits(resTemp, high, low, midRes); 564 } 565 Dest = resTemp; 566 ''', flagType="none", buildCc=False) 567 buildRegDataInst("uqadd8", ''' 568 uint32_t midRes; 569 for (unsigned i = 0; i < 4; i++) { 570 int high = (i + 1) * 8 - 1; 571 int low = i * 8; 572 uint64_t arg1 = bits(Op1, high, low); 573 uint64_t arg2 = bits(Op2, high, low); 574 uSaturateOp<8>(midRes, arg1, arg2); 575 replaceBits(resTemp, high, low, midRes); 576 } 577 Dest = resTemp; 578 ''', flagType="none", buildCc=False) 579 buildRegDataInst("uqsub16", ''' 580 uint32_t midRes; 581 for (unsigned i = 0; i < 2; i++) { 582 int high = (i + 1) * 16 - 1; 583 int low = i * 16; 584 uint64_t arg1 = bits(Op1, high, low); 585 uint64_t arg2 = bits(Op2, high, low); 586 uSaturateOp<16>(midRes, arg1, arg2, true); 587 replaceBits(resTemp, high, low, midRes); 588 } 589 Dest = resTemp; 590 ''', flagType="none", buildCc=False) 591 buildRegDataInst("uqsub8", ''' 592 uint32_t midRes; 593 for (unsigned i = 0; i < 4; i++) { 594 int high = (i + 1) * 8 - 1; 595 int low = i * 8; 596 uint64_t arg1 = bits(Op1, high, low); 597 uint64_t arg2 = bits(Op2, high, low); 598 uSaturateOp<8>(midRes, arg1, arg2, true); 599 replaceBits(resTemp, high, low, midRes); 600 } 601 Dest = resTemp; 602 ''', flagType="none", buildCc=False) 603 buildRegDataInst("uqasx", ''' 604 uint32_t midRes; 605 uint64_t arg1Low = bits(Op1.sw, 15, 0); 606 uint64_t arg1High = bits(Op1.sw, 31, 16); 607 uint64_t arg2Low = bits(Op2.sw, 15, 0); 608 uint64_t arg2High = bits(Op2.sw, 31, 16); 609 uSaturateOp<16>(midRes, arg1Low, arg2High, true); 610 replaceBits(resTemp, 15, 0, midRes); 611 uSaturateOp<16>(midRes, arg1High, arg2Low); 612 replaceBits(resTemp, 31, 16, midRes); 613 Dest = resTemp; 614 ''', flagType="none", buildCc=False) 615 buildRegDataInst("uqsax", ''' 616 uint32_t midRes; 617 uint64_t arg1Low = bits(Op1.sw, 15, 0); 618 uint64_t arg1High = bits(Op1.sw, 31, 16); 619 uint64_t arg2Low = bits(Op2.sw, 15, 0); 620 uint64_t arg2High = bits(Op2.sw, 31, 16); 621 uSaturateOp<16>(midRes, arg1Low, arg2High); 622 replaceBits(resTemp, 15, 0, midRes); 623 uSaturateOp<16>(midRes, arg1High, arg2Low, true); 624 replaceBits(resTemp, 31, 16, midRes); 625 Dest = resTemp; 626 ''', flagType="none", buildCc=False) 627 628 buildRegDataInst("uadd16", ''' 629 uint32_t geBits = 0; 630 resTemp = 0; 631 for (unsigned i = 0; i < 2; i++) { 632 int high = (i + 1) * 16 - 1; 633 int low = i * 16; 634 int32_t midRes = bits(Op1, high, low) + 635 bits(Op2, high, low); 636 if (midRes >= 0x10000) { 637 geBits = geBits | (0x3 << (i * 2)); 638 } 639 replaceBits(resTemp, high, low, midRes); 640 } 641 Dest = resTemp; 642 resTemp = geBits; 643 ''', flagType="ge", buildNonCc=False) 644 buildRegDataInst("uadd8", ''' 645 uint32_t geBits = 0; 646 resTemp = 0; 647 for (unsigned i = 0; i < 4; i++) { 648 int high = (i + 1) * 8 - 1; 649 int low = i * 8; 650 int32_t midRes = bits(Op1, high, low) + 651 bits(Op2, high, low); 652 if (midRes >= 0x100) { 653 geBits = geBits | (1 << i); 654 } 655 replaceBits(resTemp, high, low, midRes); 656 } 657 Dest = resTemp; 658 resTemp = geBits; 659 ''', flagType="ge", buildNonCc=False) 660 buildRegDataInst("usub16", ''' 661 uint32_t geBits = 0; 662 resTemp = 0; 663 for (unsigned i = 0; i < 2; i++) { 664 int high = (i + 1) * 16 - 1; 665 int low = i * 16; 666 int32_t midRes = bits(Op1, high, low) - 667 bits(Op2, high, low); 668 if (midRes >= 0) { 669 geBits = geBits | (0x3 << (i * 2)); 670 } 671 replaceBits(resTemp, high, low, midRes); 672 } 673 Dest = resTemp; 674 resTemp = geBits; 675 ''', flagType="ge", buildNonCc=False) 676 buildRegDataInst("usub8", ''' 677 uint32_t geBits = 0; 678 resTemp = 0; 679 for (unsigned i = 0; i < 4; i++) { 680 int high = (i + 1) * 8 - 1; 681 int low = i * 8; 682 int32_t midRes = bits(Op1, high, low) - 683 bits(Op2, high, low); 684 if (midRes >= 0) { 685 geBits = geBits | (1 << i); 686 } 687 replaceBits(resTemp, high, low, midRes); 688 } 689 Dest = resTemp; 690 resTemp = geBits; 691 ''', flagType="ge", buildNonCc=False) 692 buildRegDataInst("uasx", ''' 693 int32_t midRes, geBits = 0; 694 resTemp = 0; 695 int64_t arg1Low = bits(Op1.sw, 15, 0); 696 int64_t arg1High = bits(Op1.sw, 31, 16); 697 int64_t arg2Low = bits(Op2.sw, 15, 0); 698 int64_t arg2High = bits(Op2.sw, 31, 16); 699 midRes = arg1Low - arg2High; 700 if (midRes >= 0) { 701 geBits = geBits | 0x3; 702 } 703 replaceBits(resTemp, 15, 0, midRes); 704 midRes = arg1High + arg2Low; 705 if (midRes >= 0x10000) { 706 geBits = geBits | 0xc; 707 } 708 replaceBits(resTemp, 31, 16, midRes); 709 Dest = resTemp; 710 resTemp = geBits; 711 ''', flagType="ge", buildNonCc=False) 712 buildRegDataInst("usax", ''' 713 int32_t midRes, geBits = 0; 714 resTemp = 0; 715 int64_t arg1Low = bits(Op1.sw, 15, 0); 716 int64_t arg1High = bits(Op1.sw, 31, 16); 717 int64_t arg2Low = bits(Op2.sw, 15, 0); 718 int64_t arg2High = bits(Op2.sw, 31, 16); 719 midRes = arg1Low + arg2High; 720 if (midRes >= 0x10000) { 721 geBits = geBits | 0x3; 722 } 723 replaceBits(resTemp, 15, 0, midRes); 724 midRes = arg1High - arg2Low; 725 if (midRes >= 0) { 726 geBits = geBits | 0xc; 727 } 728 replaceBits(resTemp, 31, 16, midRes); 729 Dest = resTemp; 730 resTemp = geBits; 731 ''', flagType="ge", buildNonCc=False) 732 733 buildRegDataInst("uhadd16", ''' 734 resTemp = 0; 735 for (unsigned i = 0; i < 2; i++) { 736 int high = (i + 1) * 16 - 1; 737 int low = i * 16; 738 int32_t midRes = (bits(Op1, high, low) + 739 bits(Op2, high, low)) >> 1; 740 replaceBits(resTemp, high, low, midRes); 741 } 742 Dest = resTemp; 743 ''', flagType="none", buildCc=False) 744 buildRegDataInst("uhadd8", ''' 745 resTemp = 0; 746 for (unsigned i = 0; i < 4; i++) { 747 int high = (i + 1) * 8 - 1; 748 int low = i * 8; 749 int32_t midRes = (bits(Op1, high, low) + 750 bits(Op2, high, low)) >> 1; 751 replaceBits(resTemp, high, low, midRes); 752 } 753 Dest = resTemp; 754 ''', flagType="none", buildCc=False) 755 buildRegDataInst("uhsub16", ''' 756 resTemp = 0; 757 for (unsigned i = 0; i < 2; i++) { 758 int high = (i + 1) * 16 - 1; 759 int low = i * 16; 760 int32_t midRes = (bits(Op1, high, low) - 761 bits(Op2, high, low)) >> 1; 762 replaceBits(resTemp, high, low, midRes); 763 } 764 Dest = resTemp; 765 ''', flagType="none", buildCc=False) 766 buildRegDataInst("uhsub8", ''' 767 resTemp = 0; 768 for (unsigned i = 0; i < 4; i++) { 769 int high = (i + 1) * 8 - 1; 770 int low = i * 8; 771 int32_t midRes = (bits(Op1, high, low) - 772 bits(Op2, high, low)) >> 1; 773 replaceBits(resTemp, high, low, midRes); 774 } 775 Dest = resTemp; 776 ''', flagType="none", buildCc=False) 777 buildRegDataInst("uhasx", ''' 778 int32_t midRes; 779 resTemp = 0; 780 int64_t arg1Low = bits(Op1.sw, 15, 0); 781 int64_t arg1High = bits(Op1.sw, 31, 16); 782 int64_t arg2Low = bits(Op2.sw, 15, 0); 783 int64_t arg2High = bits(Op2.sw, 31, 16); 784 midRes = (arg1Low - arg2High) >> 1; 785 replaceBits(resTemp, 15, 0, midRes); 786 midRes = (arg1High + arg2Low) >> 1; 787 replaceBits(resTemp, 31, 16, midRes); 788 Dest = resTemp; 789 ''', flagType="none", buildCc=False) 790 buildRegDataInst("uhsax", ''' 791 int32_t midRes; 792 resTemp = 0; 793 int64_t arg1Low = bits(Op1.sw, 15, 0); 794 int64_t arg1High = bits(Op1.sw, 31, 16); 795 int64_t arg2Low = bits(Op2.sw, 15, 0); 796 int64_t arg2High = bits(Op2.sw, 31, 16); 797 midRes = (arg1Low + arg2High) >> 1; 798 replaceBits(resTemp, 15, 0, midRes); 799 midRes = (arg1High - arg2Low) >> 1; 800 replaceBits(resTemp, 31, 16, midRes); 801 Dest = resTemp; 802 ''', flagType="none", buildCc=False) 803 804 buildRegDataInst("pkhbt", ''' 805 uint32_t resTemp = 0; 806 uint16_t arg1Low = bits(Op1, 15, 0); 807 uint16_t arg2High = bits(secondOp, 31, 16); 808 replaceBits(resTemp, 15, 0, arg1Low); 809 replaceBits(resTemp, 31, 16, arg2High); 810 Dest = resTemp; 811 ''', flagType="none", buildCc=False) 812 buildRegDataInst("pkhtb", ''' 813 uint32_t resTemp = 0; 814 uint16_t arg1High = bits(Op1, 31, 16); 815 uint16_t arg2Low = bits(secondOp, 15, 0); 816 replaceBits(resTemp, 15, 0, arg2Low); 817 replaceBits(resTemp, 31, 16, arg1High); 818 Dest = resTemp; 819 ''', flagType="none", buildCc=False) 820}}; 821