data.isa revision 7214:9eba696c4592 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    calcGECode = '''
47        CondCodes = insertBits(CondCodes, 19, 16, resTemp);
48    '''
49
50    calcQCode = '''
51        CondCodes = CondCodes | ((resTemp & 1) << 27);
52    '''
53
54    calcCcCode = '''
55        uint16_t _ic, _iv, _iz, _in;
56        _in = (resTemp >> %(negBit)d) & 1;
57        _iz = (resTemp == 0);
58        _iv = %(ivValue)s & 1;
59        _ic = %(icValue)s & 1;
60
61        CondCodes =  _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
62                    (CondCodes & 0x0FFFFFFF);
63
64        DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
65                     _in, _iz, _ic, _iv);
66       '''
67
68    # Dict of code to set the carry flag. (imm, reg, reg-reg)
69    oldC = 'CondCodes<29:>'
70    oldV = 'CondCodes<28:>'
71    carryCode = {
72        "none": (oldC, oldC, oldC),
73        "llbit": (oldC, oldC, oldC),
74        "saturate": ('0', '0', '0'),
75        "overflow": ('0', '0', '0'),
76        "add": ('findCarry(32, resTemp, Op1, secondOp)',
77                'findCarry(32, resTemp, Op1, secondOp)',
78                'findCarry(32, resTemp, Op1, secondOp)'),
79        "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
80                'findCarry(32, resTemp, Op1, ~secondOp)',
81                'findCarry(32, resTemp, Op1, ~secondOp)'),
82        "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
83                'findCarry(32, resTemp, secondOp, ~Op1)',
84                'findCarry(32, resTemp, secondOp, ~Op1)'),
85        "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
86                  'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
87                  'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
88    }
89    # Dict of code to set the overflow flag.
90    overflowCode = {
91        "none": oldV,
92        "llbit": oldV,
93        "saturate": '0',
94        "overflow": '0',
95        "add": 'findOverflow(32, resTemp, Op1, secondOp)',
96        "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
97        "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
98        "logic": oldV
99    }
100
101    secondOpRe = re.compile("secondOp")
102    immOp2 = "imm"
103    regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
104    regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
105
106    def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
107                         buildCc = True, buildNonCc = True):
108        cCode = carryCode[flagType]
109        vCode = overflowCode[flagType]
110        negBit = 31
111        if flagType == "llbit":
112            negBit = 63
113        if flagType == "saturate":
114            immCcCode = calcQCode
115        elif flagType == "ge":
116            immCcCode = calcGECode
117        else:
118            immCcCode = calcCcCode % {
119                "icValue": secondOpRe.sub(immOp2, cCode[0]),
120                "ivValue": secondOpRe.sub(immOp2, vCode),
121                "negBit": negBit
122            }
123        immCode = secondOpRe.sub(immOp2, code)
124        immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
125                               {"code" : immCode,
126                                "predicate_test": predicateTest})
127        immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
128                                 "DataImmOp",
129                                 {"code" : immCode + immCcCode,
130                                  "predicate_test": predicateTest})
131
132        def subst(iop):
133            global header_output, decoder_output, exec_output
134            header_output += DataImmDeclare.subst(iop)
135            decoder_output += DataImmConstructor.subst(iop)
136            exec_output += PredOpExecute.subst(iop)
137
138        if buildNonCc:
139            subst(immIop)
140        if buildCc:
141            subst(immIopCc)
142
143    def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
144                         buildCc = True, buildNonCc = True):
145        cCode = carryCode[flagType]
146        vCode = overflowCode[flagType]
147        negBit = 31
148        if flagType == "llbit":
149            negBit = 63
150        if flagType == "saturate":
151            regCcCode = calcQCode
152        elif flagType == "ge":
153            immCcCode = calcGECode
154        else:
155            regCcCode = calcCcCode % {
156                "icValue": secondOpRe.sub(regOp2, cCode[1]),
157                "ivValue": secondOpRe.sub(regOp2, vCode),
158                "negBit": negBit
159            }
160        regCode = secondOpRe.sub(regOp2, code)
161        regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
162                               {"code" : regCode,
163                                "predicate_test": predicateTest})
164        regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
165                                 "DataRegOp",
166                                 {"code" : regCode + regCcCode,
167                                  "predicate_test": predicateTest})
168
169        def subst(iop):
170            global header_output, decoder_output, exec_output
171            header_output += DataRegDeclare.subst(iop)
172            decoder_output += DataRegConstructor.subst(iop)
173            exec_output += PredOpExecute.subst(iop)
174
175        if buildNonCc:
176            subst(regIop)
177        if buildCc:
178            subst(regIopCc)
179
180    def buildRegRegDataInst(mnem, code, flagType = "logic", \
181                            suffix = "RegReg", \
182                            buildCc = True, buildNonCc = True):
183        cCode = carryCode[flagType]
184        vCode = overflowCode[flagType]
185        negBit = 31
186        if flagType == "llbit":
187            negBit = 63
188        if flagType == "saturate":
189            regRegCcCode = calcQCode
190        elif flagType == "ge":
191            immCcCode = calcGECode
192        else:
193            regRegCcCode = calcCcCode % {
194                "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
195                "ivValue": secondOpRe.sub(regRegOp2, vCode),
196                "negBit": negBit
197            }
198        regRegCode = secondOpRe.sub(regRegOp2, code)
199        regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
200                                  "DataRegRegOp",
201                                  {"code" : regRegCode,
202                                   "predicate_test": predicateTest})
203        regRegIopCc = InstObjParams(mnem + "s",
204                                    mnem.capitalize() + suffix + "Cc",
205                                    "DataRegRegOp",
206                                    {"code" : regRegCode + regRegCcCode,
207                                     "predicate_test": predicateTest})
208
209        def subst(iop):
210            global header_output, decoder_output, exec_output
211            header_output += DataRegRegDeclare.subst(iop)
212            decoder_output += DataRegRegConstructor.subst(iop)
213            exec_output += PredOpExecute.subst(iop)
214
215        if buildNonCc:
216            subst(regRegIop)
217        if buildCc:
218            subst(regRegIopCc)
219
220    def buildDataInst(mnem, code, flagType = "logic", \
221                      aiw = True, regRegAiw = True,
222                      subsPcLr = True):
223        regRegCode = instCode = code
224        if aiw:
225            instCode = "AIW" + instCode
226            if regRegAiw:
227                regRegCode = "AIW" + regRegCode
228
229        buildImmDataInst(mnem, instCode, flagType)
230        buildRegDataInst(mnem, instCode, flagType)
231        buildRegRegDataInst(mnem, regRegCode, flagType)
232        if subsPcLr:
233            code += '''
234            uint32_t newCpsr =
235                cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
236            Cpsr = ~CondCodesMask & newCpsr;
237            CondCodes = CondCodesMask & newCpsr;
238            '''
239            buildImmDataInst(mnem + 's', code, flagType,
240                             suffix = "ImmPclr", buildCc = False)
241            buildRegDataInst(mnem + 's', code, flagType,
242                             suffix = "RegPclr", buildCc = False)
243
244    buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
245    buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
246    buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
247    buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
248    buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
249    buildImmDataInst("adr", '''
250                               Dest = resTemp = (readPC(xc) & ~0x3) +
251                               (op1 ? secondOp : -secondOp);
252                            ''')
253    buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
254    buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
255    buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
256    buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
257    buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
258    buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
259    buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
260    buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
261    buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
262    buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
263    buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
264    buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
265    buildDataInst("movt",
266                  "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
267                  aiw = False)
268
269    buildRegDataInst("qadd", '''
270            int32_t midRes;
271            resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
272                                     Dest = midRes;
273        ''', flagType="saturate", buildNonCc=False)
274    buildRegDataInst("qadd16", '''
275            int32_t midRes;
276            for (unsigned i = 0; i < 2; i++) {
277                int high = (i + 1) * 16 - 1;
278                int low = i * 16;
279                int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
280                int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
281                saturateOp<16>(midRes, arg1, arg2);
282                replaceBits(resTemp, high, low, midRes);
283            }
284            Dest = resTemp;
285        ''', flagType="none", buildCc=False)
286    buildRegDataInst("qadd8", '''
287            int32_t midRes;
288            for (unsigned i = 0; i < 4; i++) {
289                int high = (i + 1) * 8 - 1;
290                int low = i * 8;
291                int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
292                int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
293                saturateOp<8>(midRes, arg1, arg2);
294                replaceBits(resTemp, high, low, midRes);
295            }
296            Dest = resTemp;
297        ''', flagType="none", buildCc=False)
298    buildRegDataInst("qdadd", '''
299            int32_t midRes;
300            resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
301                      saturateOp<32>(midRes, Op1.sw, midRes);
302            Dest = midRes;
303        ''', flagType="saturate", buildNonCc=False)
304    buildRegDataInst("qsub", '''
305            int32_t midRes;
306            resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
307            Dest = midRes;
308        ''', flagType="saturate")
309    buildRegDataInst("qsub16", '''
310            int32_t midRes;
311            for (unsigned i = 0; i < 2; i++) {
312                 int high = (i + 1) * 16 - 1;
313                 int low = i * 16;
314                 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
315                 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
316                 saturateOp<16>(midRes, arg1, arg2, true);
317                 replaceBits(resTemp, high, low, midRes);
318            }
319            Dest = resTemp;
320        ''', flagType="none", buildCc=False)
321    buildRegDataInst("qsub8", '''
322            int32_t midRes;
323            for (unsigned i = 0; i < 4; i++) {
324                 int high = (i + 1) * 8 - 1;
325                 int low = i * 8;
326                 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
327                 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
328                 saturateOp<8>(midRes, arg1, arg2, true);
329                 replaceBits(resTemp, high, low, midRes);
330            }
331            Dest = resTemp;
332        ''', flagType="none", buildCc=False)
333    buildRegDataInst("qdsub", '''
334            int32_t midRes;
335            resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
336                      saturateOp<32>(midRes, Op1.sw, midRes, true);
337            Dest = midRes;
338        ''', flagType="saturate", buildNonCc=False)
339    buildRegDataInst("qasx", '''
340            int32_t midRes;
341            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
342            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
343            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
344            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
345            saturateOp<16>(midRes, arg1Low, arg2High, true);
346            replaceBits(resTemp, 15, 0, midRes);
347            saturateOp<16>(midRes, arg1High, arg2Low);
348            replaceBits(resTemp, 31, 16, midRes);
349            Dest = resTemp;
350        ''', flagType="none", buildCc=False)
351    buildRegDataInst("qsax", '''
352            int32_t midRes;
353            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
354            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
355            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
356            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
357            saturateOp<16>(midRes, arg1Low, arg2High);
358            replaceBits(resTemp, 15, 0, midRes);
359            saturateOp<16>(midRes, arg1High, arg2Low, true);
360            replaceBits(resTemp, 31, 16, midRes);
361            Dest = resTemp;
362        ''', flagType="none", buildCc=False)
363}};
364