data.isa revision 7193:91b7045a2d4b 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    calcQCode = '''
47        CondCodes = CondCodes | ((resTemp & 1) << 27);
48    '''
49
50    calcCcCode = '''
51        uint16_t _ic, _iv, _iz, _in;
52        _in = (resTemp >> %(negBit)d) & 1;
53        _iz = (resTemp == 0);
54        _iv = %(ivValue)s & 1;
55        _ic = %(icValue)s & 1;
56
57        CondCodes =  _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
58                    (CondCodes & 0x0FFFFFFF);
59
60        DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
61                     _in, _iz, _ic, _iv);
62       '''
63
64    # Dict of code to set the carry flag. (imm, reg, reg-reg)
65    oldC = 'CondCodes<29:>'
66    oldV = 'CondCodes<28:>'
67    carryCode = {
68        "none": (oldC, oldC, oldC),
69        "llbit": (oldC, oldC, oldC),
70        "saturate": ('0', '0', '0'),
71        "overflow": ('0', '0', '0'),
72        "add": ('findCarry(32, resTemp, Op1, secondOp)',
73                'findCarry(32, resTemp, Op1, secondOp)',
74                'findCarry(32, resTemp, Op1, secondOp)'),
75        "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
76                'findCarry(32, resTemp, Op1, ~secondOp)',
77                'findCarry(32, resTemp, Op1, ~secondOp)'),
78        "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
79                'findCarry(32, resTemp, secondOp, ~Op1)',
80                'findCarry(32, resTemp, secondOp, ~Op1)'),
81        "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
82                  'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
83                  'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
84    }
85    # Dict of code to set the overflow flag.
86    overflowCode = {
87        "none": oldV,
88        "llbit": oldV,
89        "saturate": '0',
90        "overflow": '0',
91        "add": 'findOverflow(32, resTemp, Op1, secondOp)',
92        "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
93        "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
94        "logic": oldV
95    }
96
97    secondOpRe = re.compile("secondOp")
98    immOp2 = "imm"
99    regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
100    regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
101
102    def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
103                         buildCc = True, buildNonCc = True):
104        cCode = carryCode[flagType]
105        vCode = overflowCode[flagType]
106        negBit = 31
107        if flagType == "llbit":
108            negBit = 63
109        if flagType == "saturate":
110            immCcCode = calcQCode
111        else:
112            immCcCode = calcCcCode % {
113                "icValue": secondOpRe.sub(immOp2, cCode[0]),
114                "ivValue": secondOpRe.sub(immOp2, vCode),
115                "negBit": negBit
116            }
117        immCode = secondOpRe.sub(immOp2, code)
118        immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
119                               {"code" : immCode,
120                                "predicate_test": predicateTest})
121        immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
122                                 "DataImmOp",
123                                 {"code" : immCode + immCcCode,
124                                  "predicate_test": predicateTest})
125
126        def subst(iop):
127            global header_output, decoder_output, exec_output
128            header_output += DataImmDeclare.subst(iop)
129            decoder_output += DataImmConstructor.subst(iop)
130            exec_output += PredOpExecute.subst(iop)
131
132        if buildNonCc:
133            subst(immIop)
134        if buildCc:
135            subst(immIopCc)
136
137    def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
138                         buildCc = True, buildNonCc = True):
139        cCode = carryCode[flagType]
140        vCode = overflowCode[flagType]
141        negBit = 31
142        if flagType == "llbit":
143            negBit = 63
144        if flagType == "saturate":
145            regCcCode = calcQCode
146        else:
147            regCcCode = calcCcCode % {
148                "icValue": secondOpRe.sub(regOp2, cCode[1]),
149                "ivValue": secondOpRe.sub(regOp2, vCode),
150                "negBit": negBit
151            }
152        regCode = secondOpRe.sub(regOp2, code)
153        regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
154                               {"code" : regCode,
155                                "predicate_test": predicateTest})
156        regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
157                                 "DataRegOp",
158                                 {"code" : regCode + regCcCode,
159                                  "predicate_test": predicateTest})
160
161        def subst(iop):
162            global header_output, decoder_output, exec_output
163            header_output += DataRegDeclare.subst(iop)
164            decoder_output += DataRegConstructor.subst(iop)
165            exec_output += PredOpExecute.subst(iop)
166
167        if buildNonCc:
168            subst(regIop)
169        if buildCc:
170            subst(regIopCc)
171
172    def buildRegRegDataInst(mnem, code, flagType = "logic", \
173                            suffix = "RegReg", \
174                            buildCc = True, buildNonCc = True):
175        cCode = carryCode[flagType]
176        vCode = overflowCode[flagType]
177        negBit = 31
178        if flagType == "llbit":
179            negBit = 63
180        if flagType == "saturate":
181            regRegCcCode = calcQCode
182        else:
183            regRegCcCode = calcCcCode % {
184                "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
185                "ivValue": secondOpRe.sub(regRegOp2, vCode),
186                "negBit": negBit
187            }
188        regRegCode = secondOpRe.sub(regRegOp2, code)
189        regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
190                                  "DataRegRegOp",
191                                  {"code" : regRegCode,
192                                   "predicate_test": predicateTest})
193        regRegIopCc = InstObjParams(mnem + "s",
194                                    mnem.capitalize() + suffix + "Cc",
195                                    "DataRegRegOp",
196                                    {"code" : regRegCode + regRegCcCode,
197                                     "predicate_test": predicateTest})
198
199        def subst(iop):
200            global header_output, decoder_output, exec_output
201            header_output += DataRegRegDeclare.subst(iop)
202            decoder_output += DataRegRegConstructor.subst(iop)
203            exec_output += PredOpExecute.subst(iop)
204
205        if buildNonCc:
206            subst(regRegIop)
207        if buildCc:
208            subst(regRegIopCc)
209
210    def buildDataInst(mnem, code, flagType = "logic", \
211                      aiw = True, regRegAiw = True,
212                      subsPcLr = True):
213        regRegCode = instCode = code
214        if aiw:
215            instCode = "AIW" + instCode
216            if regRegAiw:
217                regRegCode = "AIW" + regRegCode
218
219        buildImmDataInst(mnem, instCode, flagType)
220        buildRegDataInst(mnem, instCode, flagType)
221        buildRegRegDataInst(mnem, regRegCode, flagType)
222        if subsPcLr:
223            code += '''
224            uint32_t newCpsr =
225                cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
226            Cpsr = ~CondCodesMask & newCpsr;
227            CondCodes = CondCodesMask & newCpsr;
228            '''
229            buildImmDataInst(mnem + 's', code, flagType,
230                             suffix = "ImmPclr", buildCc = False)
231            buildRegDataInst(mnem + 's', code, flagType,
232                             suffix = "RegPclr", buildCc = False)
233
234    buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
235    buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
236    buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
237    buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
238    buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
239    buildImmDataInst("adr", '''
240                               Dest = resTemp = (readPC(xc) & ~0x3) +
241                               (op1 ? secondOp : -secondOp);
242                            ''')
243    buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
244    buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
245    buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
246    buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
247    buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
248    buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
249    buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
250    buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
251    buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
252    buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
253    buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
254    buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
255    buildDataInst("movt",
256                  "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
257                  aiw = False)
258
259    buildRegDataInst("qadd", '''
260            int32_t midRes;
261            resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
262                                     Dest = midRes;
263        ''', flagType="saturate", buildNonCc=False)
264    buildRegDataInst("qadd16", '''
265            int32_t midRes;
266            for (unsigned i = 0; i < 2; i++) {
267                int high = (i + 1) * 16 - 1;
268                int low = i * 16;
269                int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
270                int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
271                saturateOp<16>(midRes, arg1, arg2);
272                replaceBits(resTemp, high, low, midRes);
273            }
274            Dest = resTemp;
275        ''', flagType="none", buildCc=False)
276    buildRegDataInst("qadd8", '''
277            int32_t midRes;
278            for (unsigned i = 0; i < 4; i++) {
279                int high = (i + 1) * 8 - 1;
280                int low = i * 8;
281                int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
282                int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
283                saturateOp<8>(midRes, arg1, arg2);
284                replaceBits(resTemp, high, low, midRes);
285            }
286            Dest = resTemp;
287        ''', flagType="none", buildCc=False)
288    buildRegDataInst("qdadd", '''
289            int32_t midRes;
290            resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
291                      saturateOp<32>(midRes, Op1.sw, midRes);
292            Dest = midRes;
293        ''', flagType="saturate", buildNonCc=False)
294    buildRegDataInst("qsub", '''
295            int32_t midRes;
296            resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
297            Dest = midRes;
298        ''', flagType="saturate")
299    buildRegDataInst("qsub16", '''
300            int32_t midRes;
301            for (unsigned i = 0; i < 2; i++) {
302                 int high = (i + 1) * 16 - 1;
303                 int low = i * 16;
304                 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
305                 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
306                 saturateOp<16>(midRes, arg1, arg2, true);
307                 replaceBits(resTemp, high, low, midRes);
308            }
309            Dest = resTemp;
310        ''', flagType="none", buildCc=False)
311    buildRegDataInst("qsub8", '''
312            int32_t midRes;
313            for (unsigned i = 0; i < 4; i++) {
314                 int high = (i + 1) * 8 - 1;
315                 int low = i * 8;
316                 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
317                 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
318                 saturateOp<8>(midRes, arg1, arg2, true);
319                 replaceBits(resTemp, high, low, midRes);
320            }
321            Dest = resTemp;
322        ''', flagType="none", buildCc=False)
323    buildRegDataInst("qdsub", '''
324            int32_t midRes;
325            resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
326                      saturateOp<32>(midRes, Op1.sw, midRes, true);
327            Dest = midRes;
328        ''', flagType="saturate", buildNonCc=False)
329    buildRegDataInst("qasx", '''
330            int32_t midRes;
331            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
332            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
333            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
334            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
335            saturateOp<16>(midRes, arg1Low, arg2High, true);
336            replaceBits(resTemp, 15, 0, midRes);
337            saturateOp<16>(midRes, arg1High, arg2Low);
338            replaceBits(resTemp, 31, 16, midRes);
339            Dest = resTemp;
340        ''', flagType="none", buildCc=False)
341    buildRegDataInst("qsax", '''
342            int32_t midRes;
343            int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
344            int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
345            int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
346            int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
347            saturateOp<16>(midRes, arg1Low, arg2High);
348            replaceBits(resTemp, 15, 0, midRes);
349            saturateOp<16>(midRes, arg1High, arg2Low, true);
350            replaceBits(resTemp, 31, 16, midRes);
351            Dest = resTemp;
352        ''', flagType="none", buildCc=False)
353}};
354