data.isa revision 7184
17138Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27138Sgblack@eecs.umich.edu 37138Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47138Sgblack@eecs.umich.edu// All rights reserved 57138Sgblack@eecs.umich.edu// 67138Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77138Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87138Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97138Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107138Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117138Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127138Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137138Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147138Sgblack@eecs.umich.edu// 157138Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167138Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177138Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187138Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197138Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207138Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217138Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227138Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237138Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247138Sgblack@eecs.umich.edu// this software without specific prior written permission. 257138Sgblack@eecs.umich.edu// 267138Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277138Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287138Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297138Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307138Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317138Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327138Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337138Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347138Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357138Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367138Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377138Sgblack@eecs.umich.edu// 387138Sgblack@eecs.umich.edu// Authors: Gabe Black 397138Sgblack@eecs.umich.edu 407138Sgblack@eecs.umich.edulet {{ 417138Sgblack@eecs.umich.edu 427138Sgblack@eecs.umich.edu header_output = "" 437138Sgblack@eecs.umich.edu decoder_output = "" 447138Sgblack@eecs.umich.edu exec_output = "" 457138Sgblack@eecs.umich.edu 467138Sgblack@eecs.umich.edu calcQCode = ''' 477138Sgblack@eecs.umich.edu cprintf("canOverflow: %%d\\n", Dest < resTemp); 487138Sgblack@eecs.umich.edu replaceBits(CondCodes, 27, Dest < resTemp); 497138Sgblack@eecs.umich.edu ''' 507138Sgblack@eecs.umich.edu 517138Sgblack@eecs.umich.edu calcCcCode = ''' 527138Sgblack@eecs.umich.edu uint16_t _ic, _iv, _iz, _in; 537138Sgblack@eecs.umich.edu _in = (resTemp >> %(negBit)d) & 1; 547138Sgblack@eecs.umich.edu _iz = (resTemp == 0); 557138Sgblack@eecs.umich.edu _iv = %(ivValue)s & 1; 567138Sgblack@eecs.umich.edu _ic = %(icValue)s & 1; 577138Sgblack@eecs.umich.edu 587138Sgblack@eecs.umich.edu CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 597138Sgblack@eecs.umich.edu (CondCodes & 0x0FFFFFFF); 607138Sgblack@eecs.umich.edu 617138Sgblack@eecs.umich.edu DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", 627138Sgblack@eecs.umich.edu _in, _iz, _ic, _iv); 637138Sgblack@eecs.umich.edu ''' 647138Sgblack@eecs.umich.edu 657138Sgblack@eecs.umich.edu # Dict of code to set the carry flag. (imm, reg, reg-reg) 667138Sgblack@eecs.umich.edu oldC = 'CondCodes<29:>' 677138Sgblack@eecs.umich.edu oldV = 'CondCodes<28:>' 687138Sgblack@eecs.umich.edu carryCode = { 697138Sgblack@eecs.umich.edu "none": (oldC, oldC, oldC), 707138Sgblack@eecs.umich.edu "llbit": (oldC, oldC, oldC), 717138Sgblack@eecs.umich.edu "overflow": ('0', '0', '0'), 727138Sgblack@eecs.umich.edu "add": ('findCarry(32, resTemp, Op1, secondOp)', 737138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, secondOp)', 747138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, secondOp)'), 757138Sgblack@eecs.umich.edu "sub": ('findCarry(32, resTemp, Op1, ~secondOp)', 767138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, ~secondOp)', 777138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, ~secondOp)'), 787138Sgblack@eecs.umich.edu "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)', 797138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, secondOp, ~Op1)', 807138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, secondOp, ~Op1)'), 817138Sgblack@eecs.umich.edu "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC, 827138Sgblack@eecs.umich.edu 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC, 837138Sgblack@eecs.umich.edu 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC) 847138Sgblack@eecs.umich.edu } 857138Sgblack@eecs.umich.edu # Dict of code to set the overflow flag. 867138Sgblack@eecs.umich.edu overflowCode = { 877138Sgblack@eecs.umich.edu "none": oldV, 887138Sgblack@eecs.umich.edu "llbit": oldV, 897138Sgblack@eecs.umich.edu "overflow": '0', 907138Sgblack@eecs.umich.edu "add": 'findOverflow(32, resTemp, Op1, secondOp)', 917138Sgblack@eecs.umich.edu "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 927138Sgblack@eecs.umich.edu "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 937138Sgblack@eecs.umich.edu "logic": oldV 947138Sgblack@eecs.umich.edu } 957138Sgblack@eecs.umich.edu 967138Sgblack@eecs.umich.edu secondOpRe = re.compile("secondOp") 977138Sgblack@eecs.umich.edu immOp2 = "imm" 987138Sgblack@eecs.umich.edu regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 997181Sgblack@eecs.umich.edu regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 1007138Sgblack@eecs.umich.edu 1017184Sgblack@eecs.umich.edu def buildImmDataInst(mnem, code, flagType = "logic"): 1027138Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1037138Sgblack@eecs.umich.edu cCode = carryCode[flagType] 1047138Sgblack@eecs.umich.edu vCode = overflowCode[flagType] 1057138Sgblack@eecs.umich.edu negBit = 31 1067138Sgblack@eecs.umich.edu if flagType == "llbit": 1077138Sgblack@eecs.umich.edu negBit = 63 1087138Sgblack@eecs.umich.edu if flagType == "overflow": 1097184Sgblack@eecs.umich.edu immCcCode = calcQCode 1107138Sgblack@eecs.umich.edu else: 1117138Sgblack@eecs.umich.edu immCcCode = calcCcCode % { 1127138Sgblack@eecs.umich.edu "icValue": secondOpRe.sub(immOp2, cCode[0]), 1137138Sgblack@eecs.umich.edu "ivValue": secondOpRe.sub(immOp2, vCode), 1147138Sgblack@eecs.umich.edu "negBit": negBit 1157138Sgblack@eecs.umich.edu } 1167184Sgblack@eecs.umich.edu immCode = secondOpRe.sub(immOp2, code) 1177184Sgblack@eecs.umich.edu immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp", 1187184Sgblack@eecs.umich.edu {"code" : immCode, 1197184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1207184Sgblack@eecs.umich.edu immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc", 1217184Sgblack@eecs.umich.edu "DataImmOp", 1227184Sgblack@eecs.umich.edu {"code" : immCode + immCcCode, 1237184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1247184Sgblack@eecs.umich.edu header_output += DataImmDeclare.subst(immIop) + \ 1257184Sgblack@eecs.umich.edu DataImmDeclare.subst(immIopCc) 1267184Sgblack@eecs.umich.edu decoder_output += DataImmConstructor.subst(immIop) + \ 1277184Sgblack@eecs.umich.edu DataImmConstructor.subst(immIopCc) 1287184Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(immIop) + \ 1297184Sgblack@eecs.umich.edu PredOpExecute.subst(immIopCc) 1307184Sgblack@eecs.umich.edu 1317184Sgblack@eecs.umich.edu def buildRegDataInst(mnem, code, flagType = "logic"): 1327184Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1337184Sgblack@eecs.umich.edu cCode = carryCode[flagType] 1347184Sgblack@eecs.umich.edu vCode = overflowCode[flagType] 1357184Sgblack@eecs.umich.edu negBit = 31 1367184Sgblack@eecs.umich.edu if flagType == "llbit": 1377184Sgblack@eecs.umich.edu negBit = 63 1387184Sgblack@eecs.umich.edu if flagType == "overflow": 1397184Sgblack@eecs.umich.edu regCcCode = calcQCode 1407184Sgblack@eecs.umich.edu else: 1417138Sgblack@eecs.umich.edu regCcCode = calcCcCode % { 1427138Sgblack@eecs.umich.edu "icValue": secondOpRe.sub(regOp2, cCode[1]), 1437138Sgblack@eecs.umich.edu "ivValue": secondOpRe.sub(regOp2, vCode), 1447138Sgblack@eecs.umich.edu "negBit": negBit 1457138Sgblack@eecs.umich.edu } 1467184Sgblack@eecs.umich.edu regCode = secondOpRe.sub(regOp2, code) 1477184Sgblack@eecs.umich.edu regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp", 1487184Sgblack@eecs.umich.edu {"code" : regCode, 1497184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1507184Sgblack@eecs.umich.edu regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc", 1517184Sgblack@eecs.umich.edu "DataRegOp", 1527184Sgblack@eecs.umich.edu {"code" : regCode + regCcCode, 1537184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1547184Sgblack@eecs.umich.edu header_output += DataRegDeclare.subst(regIop) + \ 1557184Sgblack@eecs.umich.edu DataRegDeclare.subst(regIopCc) 1567184Sgblack@eecs.umich.edu decoder_output += DataRegConstructor.subst(regIop) + \ 1577184Sgblack@eecs.umich.edu DataRegConstructor.subst(regIopCc) 1587184Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(regIop) + \ 1597184Sgblack@eecs.umich.edu PredOpExecute.subst(regIopCc) 1607184Sgblack@eecs.umich.edu 1617184Sgblack@eecs.umich.edu def buildRegRegDataInst(mnem, code, flagType = "logic"): 1627184Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1637184Sgblack@eecs.umich.edu cCode = carryCode[flagType] 1647184Sgblack@eecs.umich.edu vCode = overflowCode[flagType] 1657184Sgblack@eecs.umich.edu negBit = 31 1667184Sgblack@eecs.umich.edu if flagType == "llbit": 1677184Sgblack@eecs.umich.edu negBit = 63 1687184Sgblack@eecs.umich.edu if flagType == "overflow": 1697184Sgblack@eecs.umich.edu regRegCcCode = calcQCode 1707184Sgblack@eecs.umich.edu else: 1717138Sgblack@eecs.umich.edu regRegCcCode = calcCcCode % { 1727138Sgblack@eecs.umich.edu "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 1737138Sgblack@eecs.umich.edu "ivValue": secondOpRe.sub(regRegOp2, vCode), 1747138Sgblack@eecs.umich.edu "negBit": negBit 1757138Sgblack@eecs.umich.edu } 1767138Sgblack@eecs.umich.edu regRegCode = secondOpRe.sub(regRegOp2, code) 1777146Sgblack@eecs.umich.edu regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg", 1787138Sgblack@eecs.umich.edu "DataRegRegOp", 1797138Sgblack@eecs.umich.edu {"code" : regRegCode, 1807138Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1817138Sgblack@eecs.umich.edu regRegIopCc = InstObjParams(mnem + "s", 1827146Sgblack@eecs.umich.edu mnem.capitalize() + "RegRegCc", 1837138Sgblack@eecs.umich.edu "DataRegRegOp", 1847138Sgblack@eecs.umich.edu {"code" : regRegCode + regRegCcCode, 1857138Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1867184Sgblack@eecs.umich.edu header_output += DataRegRegDeclare.subst(regRegIop) + \ 1877138Sgblack@eecs.umich.edu DataRegRegDeclare.subst(regRegIopCc) 1887184Sgblack@eecs.umich.edu decoder_output += DataRegRegConstructor.subst(regRegIop) + \ 1897138Sgblack@eecs.umich.edu DataRegRegConstructor.subst(regRegIopCc) 1907184Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(regRegIop) + \ 1917138Sgblack@eecs.umich.edu PredOpExecute.subst(regRegIopCc) 1927138Sgblack@eecs.umich.edu 1937184Sgblack@eecs.umich.edu def buildDataInst(mnem, code, flagType = "logic"): 1947184Sgblack@eecs.umich.edu buildImmDataInst(mnem, code, flagType) 1957184Sgblack@eecs.umich.edu buildRegDataInst(mnem, code, flagType) 1967184Sgblack@eecs.umich.edu buildRegRegDataInst(mnem, code, flagType) 1977184Sgblack@eecs.umich.edu 1987184Sgblack@eecs.umich.edu buildDataInst("and", "AIWDest = resTemp = Op1 & secondOp;") 1997184Sgblack@eecs.umich.edu buildDataInst("eor", "AIWDest = resTemp = Op1 ^ secondOp;") 2007184Sgblack@eecs.umich.edu buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub") 2017184Sgblack@eecs.umich.edu buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb") 2027184Sgblack@eecs.umich.edu buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add") 2037184Sgblack@eecs.umich.edu buildDataInst("adc", "AIWDest = resTemp = Op1 + secondOp + %s;" % oldC, 2047184Sgblack@eecs.umich.edu "add") 2057184Sgblack@eecs.umich.edu buildDataInst("sbc", "AIWDest = resTemp = Op1 - secondOp - !%s;" % oldC, 2067184Sgblack@eecs.umich.edu "sub") 2077184Sgblack@eecs.umich.edu buildDataInst("rsc", "AIWDest = resTemp = secondOp - Op1 - !%s;" % oldC, 2087184Sgblack@eecs.umich.edu "rsb") 2097138Sgblack@eecs.umich.edu buildDataInst("tst", "resTemp = Op1 & secondOp;") 2107138Sgblack@eecs.umich.edu buildDataInst("teq", "resTemp = Op1 ^ secondOp;") 2117138Sgblack@eecs.umich.edu buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub") 2127138Sgblack@eecs.umich.edu buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add") 2137184Sgblack@eecs.umich.edu buildDataInst("orr", "AIWDest = resTemp = Op1 | secondOp;") 2147138Sgblack@eecs.umich.edu buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;") 2157184Sgblack@eecs.umich.edu buildImmDataInst("mov", "AIWDest = resTemp = secondOp;") 2167184Sgblack@eecs.umich.edu buildRegDataInst("mov", "AIWDest = resTemp = secondOp;") 2177184Sgblack@eecs.umich.edu buildRegRegDataInst("mov", "Dest = resTemp = secondOp;") 2187184Sgblack@eecs.umich.edu buildDataInst("bic", "AIWDest = resTemp = Op1 & ~secondOp;") 2197184Sgblack@eecs.umich.edu buildDataInst("mvn", "AIWDest = resTemp = ~secondOp;") 2207156Sgblack@eecs.umich.edu buildDataInst("movt", 2217156Sgblack@eecs.umich.edu "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);") 2227138Sgblack@eecs.umich.edu}}; 223