crypto.isa revision 13169
113168Smatt.horsnell@arm.com// -*- mode:c++ -*- 213168Smatt.horsnell@arm.com// 313168Smatt.horsnell@arm.com// Copyright (c) 2018 ARM Limited 413168Smatt.horsnell@arm.com// All rights reserved 513168Smatt.horsnell@arm.com// 613168Smatt.horsnell@arm.com// The license below extends only to copyright in the software and shall 713168Smatt.horsnell@arm.com// not be construed as granting a license to any other intellectual 813168Smatt.horsnell@arm.com// property including but not limited to intellectual property relating 913168Smatt.horsnell@arm.com// to a hardware implementation of the functionality of the software 1013168Smatt.horsnell@arm.com// licensed hereunder. You may use the software subject to the license 1113168Smatt.horsnell@arm.com// terms below provided that you ensure that this notice is replicated 1213168Smatt.horsnell@arm.com// unmodified and in its entirety in all distributions of the software, 1313168Smatt.horsnell@arm.com// modified or unmodified, in source code or in binary form. 1413168Smatt.horsnell@arm.com// 1513168Smatt.horsnell@arm.com// Redistribution and use in source and binary forms, with or without 1613168Smatt.horsnell@arm.com// modification, are permitted provided that the following conditions are 1713168Smatt.horsnell@arm.com// met: redistributions of source code must retain the above copyright 1813168Smatt.horsnell@arm.com// notice, this list of conditions and the following disclaimer; 1913168Smatt.horsnell@arm.com// redistributions in binary form must reproduce the above copyright 2013168Smatt.horsnell@arm.com// notice, this list of conditions and the following disclaimer in the 2113168Smatt.horsnell@arm.com// documentation and/or other materials provided with the distribution; 2213168Smatt.horsnell@arm.com// neither the name of the copyright holders nor the names of its 2313168Smatt.horsnell@arm.com// contributors may be used to endorse or promote products derived from 2413168Smatt.horsnell@arm.com// this software without specific prior written permission. 2513168Smatt.horsnell@arm.com// 2613168Smatt.horsnell@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2713168Smatt.horsnell@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2813168Smatt.horsnell@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2913168Smatt.horsnell@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3013168Smatt.horsnell@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3113168Smatt.horsnell@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3213168Smatt.horsnell@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3313168Smatt.horsnell@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3413168Smatt.horsnell@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3513168Smatt.horsnell@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3613168Smatt.horsnell@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3713168Smatt.horsnell@arm.com// 3813168Smatt.horsnell@arm.com// Authors: Matt Horsnell 3913168Smatt.horsnell@arm.com// Prakash Ramrakhyani 4013168Smatt.horsnell@arm.com 4113168Smatt.horsnell@arm.comlet {{ 4213168Smatt.horsnell@arm.com 4313168Smatt.horsnell@arm.com cryptoEnabledCheckCode = ''' 4413168Smatt.horsnell@arm.com auto crypto_reg = xc->tcBase()->readMiscReg(MISCREG_ID_ISAR5); 4513168Smatt.horsnell@arm.com if (!(crypto_reg & %(mask)d)) { 4613168Smatt.horsnell@arm.com return std::make_shared<UndefinedInstruction>(machInst, true); 4713168Smatt.horsnell@arm.com } 4813168Smatt.horsnell@arm.com ''' 4913168Smatt.horsnell@arm.com 5013168Smatt.horsnell@arm.com header_output = "" 5113168Smatt.horsnell@arm.com decoder_output = "" 5213168Smatt.horsnell@arm.com exec_output = "" 5313168Smatt.horsnell@arm.com 5413168Smatt.horsnell@arm.com cryptoRegRegRegPrefix = ''' 5513168Smatt.horsnell@arm.com Crypto crypto; 5613168Smatt.horsnell@arm.com RegVect srcReg1, srcReg2, destReg; 5713168Smatt.horsnell@arm.com // Read source and destination registers. 5813168Smatt.horsnell@arm.com ''' 5913168Smatt.horsnell@arm.com for reg in range(4): 6013168Smatt.horsnell@arm.com cryptoRegRegRegPrefix += ''' 6113168Smatt.horsnell@arm.com srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 6213168Smatt.horsnell@arm.com srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 6313168Smatt.horsnell@arm.com destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 6413168Smatt.horsnell@arm.com ''' % { "reg" : reg } 6513168Smatt.horsnell@arm.com cryptoRegRegRegPrefix += ''' 6613168Smatt.horsnell@arm.com unsigned char *output = (unsigned char *)(&destReg.regs[0]); 6713168Smatt.horsnell@arm.com unsigned char *input = (unsigned char *)(&srcReg1.regs[0]); 6813168Smatt.horsnell@arm.com unsigned char *input2 = (unsigned char *)(&srcReg2.regs[0]); 6913168Smatt.horsnell@arm.com ''' 7013168Smatt.horsnell@arm.com 7113168Smatt.horsnell@arm.com cryptoSuffix = "" 7213168Smatt.horsnell@arm.com for reg in range(4): 7313168Smatt.horsnell@arm.com cryptoSuffix += ''' 7413168Smatt.horsnell@arm.com FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 7513168Smatt.horsnell@arm.com ''' % { "reg" : reg } 7613168Smatt.horsnell@arm.com 7713168Smatt.horsnell@arm.com cryptoRegRegPrefix = ''' 7813168Smatt.horsnell@arm.com Crypto crypto; 7913168Smatt.horsnell@arm.com RegVect srcReg1, destReg; 8013168Smatt.horsnell@arm.com // Read source and destination registers. 8113168Smatt.horsnell@arm.com ''' 8213168Smatt.horsnell@arm.com for reg in range(4): 8313168Smatt.horsnell@arm.com cryptoRegRegPrefix += ''' 8413168Smatt.horsnell@arm.com srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 8513168Smatt.horsnell@arm.com destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 8613168Smatt.horsnell@arm.com ''' % { "reg" : reg } 8713168Smatt.horsnell@arm.com 8813168Smatt.horsnell@arm.com cryptoRegRegPrefix += ''' 8913168Smatt.horsnell@arm.com // cast into format passed to aes encrypt method. 9013168Smatt.horsnell@arm.com unsigned char *output = (unsigned char *)(&destReg.regs[0]); 9113168Smatt.horsnell@arm.com unsigned char *input = (unsigned char *)(&srcReg1.regs[0]); 9213168Smatt.horsnell@arm.com ''' 9313168Smatt.horsnell@arm.com 9413168Smatt.horsnell@arm.com def cryptoRegRegRegInst(name, Name, opClass, enable_check, crypto_func): 9513168Smatt.horsnell@arm.com global header_output, decoder_output, exec_output 9613168Smatt.horsnell@arm.com 9713168Smatt.horsnell@arm.com crypto_prefix = enable_check + cryptoRegRegRegPrefix 9813168Smatt.horsnell@arm.com cryptocode = crypto_prefix + crypto_func + cryptoSuffix 9913168Smatt.horsnell@arm.com 10013168Smatt.horsnell@arm.com cryptoiop = InstObjParams(name, Name, "RegRegRegOp", 10113168Smatt.horsnell@arm.com { "code": cryptocode, 10213168Smatt.horsnell@arm.com "r_count": 4, 10313168Smatt.horsnell@arm.com "predicate_test": predicateTest, 10413168Smatt.horsnell@arm.com "op_class": opClass}, []) 10513168Smatt.horsnell@arm.com header_output += RegRegRegOpDeclare.subst(cryptoiop) 10613168Smatt.horsnell@arm.com decoder_output += RegRegRegOpConstructor.subst(cryptoiop) 10713168Smatt.horsnell@arm.com exec_output += CryptoPredOpExecute.subst(cryptoiop) 10813168Smatt.horsnell@arm.com 10913168Smatt.horsnell@arm.com def cryptoRegRegInst(name, Name, opClass, enable_check, crypto_func): 11013168Smatt.horsnell@arm.com global header_output, decoder_output, exec_output 11113168Smatt.horsnell@arm.com 11213168Smatt.horsnell@arm.com crypto_prefix = enable_check + cryptoRegRegPrefix 11313168Smatt.horsnell@arm.com cryptocode = crypto_prefix + crypto_func + cryptoSuffix 11413168Smatt.horsnell@arm.com 11513168Smatt.horsnell@arm.com cryptoiop = InstObjParams(name, Name, "RegRegOp", 11613168Smatt.horsnell@arm.com { "code": cryptocode, 11713168Smatt.horsnell@arm.com "r_count": 4, 11813168Smatt.horsnell@arm.com "predicate_test": predicateTest, 11913168Smatt.horsnell@arm.com "op_class": opClass}, []) 12013168Smatt.horsnell@arm.com header_output += RegRegOpDeclare.subst(cryptoiop) 12113168Smatt.horsnell@arm.com decoder_output += RegRegOpConstructor.subst(cryptoiop) 12213168Smatt.horsnell@arm.com exec_output += CryptoPredOpExecute.subst(cryptoiop) 12313168Smatt.horsnell@arm.com 12413168Smatt.horsnell@arm.com def cryptoRegRegImmInst(name, Name, opClass, enable_check, crypto_func): 12513168Smatt.horsnell@arm.com global header_output, decoder_output, exec_output 12613168Smatt.horsnell@arm.com 12713168Smatt.horsnell@arm.com crypto_prefix = enable_check + cryptoRegRegPrefix 12813168Smatt.horsnell@arm.com cryptocode = crypto_prefix + crypto_func + cryptoSuffix 12913168Smatt.horsnell@arm.com 13013168Smatt.horsnell@arm.com cryptoiop = InstObjParams(name, Name, "RegRegImmOp", 13113168Smatt.horsnell@arm.com { "code": cryptocode, 13213168Smatt.horsnell@arm.com "r_count": 4, 13313168Smatt.horsnell@arm.com "predicate_test": predicateTest, 13413168Smatt.horsnell@arm.com "op_class": opClass}, []) 13513168Smatt.horsnell@arm.com header_output += RegRegImmOpDeclare.subst(cryptoiop) 13613168Smatt.horsnell@arm.com decoder_output += RegRegImmOpConstructor.subst(cryptoiop) 13713168Smatt.horsnell@arm.com exec_output += CryptoPredOpExecute.subst(cryptoiop) 13813168Smatt.horsnell@arm.com 13913169Smatt.horsnell@arm.com aeseCode = "crypto.aesEncrypt(output, input, input2);" 14013169Smatt.horsnell@arm.com aesdCode = "crypto.aesDecrypt(output, input, input2);" 14113169Smatt.horsnell@arm.com aesmcCode = "crypto.aesMixColumns(output, input);" 14213169Smatt.horsnell@arm.com aesimcCode = "crypto.aesInvMixColumns(output, input);" 14313169Smatt.horsnell@arm.com 14413168Smatt.horsnell@arm.com sha1_cCode = "crypto.sha1C(output, input, input2);" 14513168Smatt.horsnell@arm.com sha1_pCode = "crypto.sha1P(output, input, input2);" 14613168Smatt.horsnell@arm.com sha1_mCode = "crypto.sha1M(output, input, input2);" 14713168Smatt.horsnell@arm.com sha1_hCode = "crypto.sha1H(output, input);" 14813168Smatt.horsnell@arm.com sha1_su0Code = "crypto.sha1Su0(output, input, input2);" 14913168Smatt.horsnell@arm.com sha1_su1Code = "crypto.sha1Su1(output, input);" 15013168Smatt.horsnell@arm.com 15113168Smatt.horsnell@arm.com sha256_hCode = "crypto.sha256H(output, input, input2);" 15213168Smatt.horsnell@arm.com sha256_h2Code = "crypto.sha256H2(output, input, input2);" 15313168Smatt.horsnell@arm.com sha256_su0Code = "crypto.sha256Su0(output, input);" 15413168Smatt.horsnell@arm.com sha256_su1Code = "crypto.sha256Su1(output, input, input2);" 15513168Smatt.horsnell@arm.com 15613169Smatt.horsnell@arm.com aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 } 15713169Smatt.horsnell@arm.com cryptoRegRegRegInst("aese", "AESE", "SimdAesOp", 15813169Smatt.horsnell@arm.com aes_enabled, aeseCode) 15913169Smatt.horsnell@arm.com cryptoRegRegRegInst("aesd", "AESD", "SimdAesOp", 16013169Smatt.horsnell@arm.com aes_enabled, aesdCode) 16113169Smatt.horsnell@arm.com cryptoRegRegInst("aesmc", "AESMC", "SimdAesMixOp", 16213169Smatt.horsnell@arm.com aes_enabled, aesmcCode) 16313169Smatt.horsnell@arm.com cryptoRegRegInst("aesimc", "AESIMC", "SimdAesMixOp", 16413169Smatt.horsnell@arm.com aes_enabled, aesimcCode) 16513169Smatt.horsnell@arm.com 16613168Smatt.horsnell@arm.com sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 } 16713168Smatt.horsnell@arm.com cryptoRegRegRegInst("sha1c", "SHA1C", "SimdSha1HashOp", 16813168Smatt.horsnell@arm.com sha1_enabled, sha1_cCode) 16913168Smatt.horsnell@arm.com cryptoRegRegRegInst("sha1p", "SHA1P", "SimdSha1HashOp", 17013168Smatt.horsnell@arm.com sha1_enabled, sha1_pCode) 17113168Smatt.horsnell@arm.com cryptoRegRegRegInst("sha1m", "SHA1M", "SimdSha1HashOp", 17213168Smatt.horsnell@arm.com sha1_enabled, sha1_mCode) 17313168Smatt.horsnell@arm.com cryptoRegRegInst("sha1h", "SHA1H", "SimdSha1Hash2Op", 17413168Smatt.horsnell@arm.com sha1_enabled, sha1_hCode) 17513168Smatt.horsnell@arm.com cryptoRegRegRegInst("sha1su0", "SHA1SU0", "SimdShaSigma3Op", 17613168Smatt.horsnell@arm.com sha1_enabled, sha1_su0Code) 17713168Smatt.horsnell@arm.com cryptoRegRegInst("sha1su1", "SHA1SU1", "SimdShaSigma2Op", 17813168Smatt.horsnell@arm.com sha1_enabled, sha1_su1Code) 17913168Smatt.horsnell@arm.com 18013168Smatt.horsnell@arm.com sha2_enabled = cryptoEnabledCheckCode % { "mask" : 0xF000 } 18113168Smatt.horsnell@arm.com cryptoRegRegRegInst("sha256h", "SHA256H", "SimdSha256HashOp", 18213168Smatt.horsnell@arm.com sha2_enabled, sha256_hCode) 18313168Smatt.horsnell@arm.com cryptoRegRegRegInst("sha256h2", "SHA256H2", "SimdSha256Hash2Op", 18413168Smatt.horsnell@arm.com sha2_enabled, sha256_h2Code) 18513168Smatt.horsnell@arm.com cryptoRegRegInst("sha256su0", "SHA256SU0", "SimdShaSigma2Op", 18613168Smatt.horsnell@arm.com sha2_enabled, sha256_su0Code) 18713168Smatt.horsnell@arm.com cryptoRegRegRegInst("sha256su1", "SHA256SU1", "SimdShaSigma3Op", 18813168Smatt.horsnell@arm.com sha2_enabled, sha256_su1Code) 18913168Smatt.horsnell@arm.com}}; 190