branch64.isa revision 10474:799c8ee4ecba 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39//          Giacomo Gabrielli
40
41let {{
42
43    header_output = ""
44    decoder_output = ""
45    exec_output = ""
46
47    # B, BL
48    for (mnem, link) in (("b", False), ("bl", True)):
49        bCode = ('NPC = purifyTaggedAddr(RawPC + imm, xc->tcBase(), '
50                 'currEL(xc->tcBase()));\n')
51        instFlags = ['IsDirectControl', 'IsUncondControl']
52        if (link):
53            bCode += 'XLR = RawPC + 4;\n'
54            instFlags += ['IsCall']
55
56        bIop = InstObjParams(mnem, mnem.capitalize() + "64",
57                             "BranchImm64", bCode, instFlags)
58        header_output += BranchImm64Declare.subst(bIop)
59        decoder_output += BranchImm64Constructor.subst(bIop)
60        exec_output += BasicExecute.subst(bIop)
61
62    # BR, BLR
63    for (mnem, link) in (("br", False), ("blr", True)):
64        bCode = ('NPC = purifyTaggedAddr(XOp1, xc->tcBase(), '
65                 'currEL(xc->tcBase()));\n')
66        instFlags = ['IsIndirectControl', 'IsUncondControl']
67        if (link):
68            bCode += 'XLR = RawPC + 4;\n'
69            instFlags += ['IsCall']
70
71        bIop = InstObjParams(mnem, mnem.capitalize() + "64",
72                             "BranchReg64", bCode, instFlags)
73        header_output += BranchReg64Declare.subst(bIop)
74        decoder_output += BranchReg64Constructor.subst(bIop)
75        exec_output += BasicExecute.subst(bIop)
76
77    # B conditional
78    bCode = '''
79        if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode))
80            NPC = purifyTaggedAddr(RawPC + imm, xc->tcBase(),
81                                   currEL(xc->tcBase()));
82        else
83            NPC = NPC;
84    '''
85    bIop = InstObjParams("b", "BCond64", "BranchImmCond64", bCode,
86                         ['IsCondControl', 'IsDirectControl'])
87    header_output += BranchImmCond64Declare.subst(bIop)
88    decoder_output += BranchImmCond64Constructor.subst(bIop)
89    exec_output += BasicExecute.subst(bIop)
90
91    # RET
92    bCode = ('NPC = purifyTaggedAddr(XOp1, xc->tcBase(), '
93             'currEL(xc->tcBase()));\n')
94    instFlags = ['IsIndirectControl', 'IsUncondControl', 'IsReturn']
95
96    bIop = InstObjParams('ret', 'Ret64', "BranchRet64", bCode, instFlags)
97    header_output += BranchReg64Declare.subst(bIop)
98    decoder_output += BranchReg64Constructor.subst(bIop)
99    exec_output += BasicExecute.subst(bIop)
100
101    # ERET
102    bCode = '''Addr newPc;
103                CPSR cpsr = Cpsr;
104                CPSR spsr = Spsr;
105
106                ExceptionLevel curr_el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
107                switch (curr_el) {
108                  case EL3:
109                    newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL3);
110                    break;
111                  case EL2:
112                    newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL2);
113                    break;
114                  case EL1:
115                    newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL1);
116                    break;
117                  default:
118                    return std::make_shared<UndefinedInstruction>(machInst,
119                                                                  false,
120                                                                  mnemonic);
121                    break;
122                }
123                if (spsr.width && (newPc & mask(2))) {
124                    // To avoid PC Alignment fault when returning to AArch32
125                    if (spsr.t)
126                        newPc = newPc & ~mask(1);
127                    else
128                        newPc = newPc & ~mask(2);
129                }
130                spsr.q = 0;
131                spsr.it1 = 0;
132                spsr.j = 0;
133                spsr.res0_23_22 = 0;
134                spsr.ge = 0;
135                spsr.it2 = 0;
136                spsr.t = 0;
137
138                OperatingMode mode = (OperatingMode) (uint8_t) spsr.mode;
139                bool illegal = false;
140                ExceptionLevel target_el;
141                if (badMode(mode)) {
142                    illegal = true;
143                } else {
144                    target_el = opModeToEL(mode);
145                    if (((target_el == EL2) &&
146                         !ArmSystem::haveVirtualization(xc->tcBase())) ||
147                            (target_el > curr_el) ||
148                            (spsr.width == 1)) {
149                        illegal = true;
150                    } else {
151                        bool known = true;
152                        bool from32 = (spsr.width == 1);
153                        bool to32 = false;
154                        if (false) { // TODO: !haveAArch32EL
155                            to32 = false;
156                        } else if (!ArmSystem::highestELIs64(xc->tcBase())) {
157                            to32 = true;
158                        } else {
159                            bool scr_rw, hcr_rw;
160                            if (ArmSystem::haveSecurity(xc->tcBase())) {
161                                SCR scr = xc->tcBase()->readMiscReg(MISCREG_SCR_EL3);
162                                scr_rw = scr.rw;
163                            } else {
164                                scr_rw = true;
165                            }
166
167                            if (ArmSystem::haveVirtualization(xc->tcBase())) {
168                                HCR hcr = xc->tcBase()->readMiscReg(MISCREG_HCR_EL2);
169                                hcr_rw = hcr.rw;
170                            } else {
171                                hcr_rw = scr_rw;
172                            }
173
174                            switch (target_el) {
175                              case EL3:
176                                to32 = false;
177                                break;
178                              case EL2:
179                                to32 = !scr_rw;
180                                break;
181                              case EL1:
182                                to32 = !scr_rw || !hcr_rw;
183                                break;
184                              case EL0:
185                                if (curr_el == EL0) {
186                                    to32 = cpsr.width;
187                                } else if (!scr_rw || !hcr_rw) {
188                                    // EL0 using AArch32 if EL1 using AArch32
189                                    to32 = true;
190                                } else {
191                                    known = false;
192                                    to32 = false;
193                                }
194                            }
195                        }
196                        if (known)
197                            illegal = (from32 != to32);
198                    }
199                }
200
201                if (illegal) {
202                    uint8_t old_mode = cpsr.mode;
203                    spsr.mode = old_mode; // Preserve old mode when invalid
204                    spsr.il = 1;
205                } else {
206                    if (cpsr.width != spsr.width)
207                        panic("AArch32/AArch64 interprocessing not supported yet");
208                }
209                Cpsr = spsr;
210
211                CondCodesNZ = spsr.nz;
212                CondCodesC  = spsr.c;
213                CondCodesV  = spsr.v;
214                NPC = purifyTaggedAddr(newPc, xc->tcBase(),
215                    opModeToEL((OperatingMode) (uint8_t) spsr.mode));
216                LLSCLock = 0;  // Clear exclusive monitor
217                SevMailbox = 1; //Set Event Register
218    '''
219    instFlags = ['IsSerializeAfter', 'IsNonSpeculative', 'IsSquashAfter']
220    bIop = InstObjParams('eret', 'Eret64', "BranchEret64", bCode, instFlags)
221    header_output += BasicDeclare.subst(bIop)
222    decoder_output += BasicConstructor64.subst(bIop)
223    exec_output += BasicExecute.subst(bIop)
224
225    # CBNZ, CBZ
226    for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
227        code = ('NPC = (Op164 %(test)s 0) ? '
228                'purifyTaggedAddr(RawPC + imm, xc->tcBase(), '
229                'currEL(xc->tcBase())) : NPC;\n')
230        code = code % {"test": test}
231        iop = InstObjParams(mnem, mnem.capitalize() + "64",
232                            "BranchImmReg64", code,
233                            ['IsCondControl', 'IsDirectControl'])
234        header_output += BranchImmReg64Declare.subst(iop)
235        decoder_output += BranchImmReg64Constructor.subst(iop)
236        exec_output += BasicExecute.subst(iop)
237
238    # TBNZ, TBZ
239    for (mnem, test) in (("tbz", "=="), ("tbnz", "!=")):
240        code = ('NPC = ((Op164 & imm1) %(test)s 0) ? '
241                'purifyTaggedAddr(RawPC + imm2, xc->tcBase(), '
242                'currEL(xc->tcBase())) : NPC;\n')
243        code = code % {"test": test}
244        iop = InstObjParams(mnem, mnem.capitalize() + "64",
245                            "BranchImmImmReg64", code,
246                            ['IsCondControl', 'IsDirectControl'])
247        header_output += BranchImmImmReg64Declare.subst(iop)
248        decoder_output += BranchImmImmReg64Constructor.subst(iop)
249        exec_output += BasicExecute.subst(iop)
250}};
251