branch.isa revision 8146:18368caa8489
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 # B, BL 47 for (mnem, link) in (("b", False), ("bl", True)): 48 bCode = ''' 49 NPC = (uint32_t)(PC + imm); 50 ''' 51 br_tgt_code = '''pcs.instNPC(branchPC.instPC() + imm);''' 52 instFlags = ["IsDirectControl"] 53 if (link): 54 bCode += ''' 55 if (Thumb) 56 LR = PC | 1; 57 else 58 LR = PC - 4; 59 ''' 60 instFlags += ["IsCall"] 61 62 63 bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond", 64 {"code": bCode, "predicate_test": predicateTest, 65 "brTgtCode" : br_tgt_code}, instFlags) 66 header_output += BranchImmCondDeclare.subst(bIop) 67 decoder_output += BranchImmCondConstructor.subst(bIop) + \ 68 BranchTarget.subst(bIop) 69 exec_output += PredOpExecute.subst(bIop) 70 71 # BX, BLX 72 blxCode = ''' 73 %(link)s 74 // Switch modes 75 %(branch)s 76 ''' 77 78 blxList = (("blx", True, True), 79 ("blx", False, True), 80 ("bx", False, False)) 81 82 for (mnem, imm, link) in blxList: 83 Name = mnem.capitalize() 84 if imm: 85 Name += "Imm" 86 # Since we're switching ISAs, the target ISA will be the opposite 87 # of the current ISA. Thumb is whether the target is ARM. 88 newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))' 89 br_tgt_code = ''' 90 pcs.instNPC((branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) : 91 (branchPC.instPC() + imm))); 92 ''' 93 base = "BranchImmCond" 94 declare = BranchImmCondDeclare 95 constructor = BranchImmCondConstructor 96 instFlags = ["IsDirectControl"] 97 else: 98 Name += "Reg" 99 newPC = 'Op1' 100 br_tgt_code = '' 101 base = "BranchRegCond" 102 declare = BranchRegCondDeclare 103 constructor = BranchRegCondConstructor 104 instFlags = ["IsIndirectControl"] 105 if link and imm: 106 linkStr = ''' 107 // The immediate version of the blx thumb instruction 108 // is 32 bits wide, but "next pc" doesn't reflect that 109 // so we don't want to substract 2 from it at this point 110 if (Thumb) 111 LR = PC | 1; 112 else 113 LR = PC - 4; 114 ''' 115 instFlags += ["IsCall"] 116 elif link: 117 linkStr = ''' 118 if (Thumb) 119 LR = (PC - 2) | 1; 120 else 121 LR = PC - 4; 122 ''' 123 instFlags += ["IsCall"] 124 else: 125 linkStr = "" 126 instFlags += ["IsReturn"] 127 128 if imm and link: #blx with imm 129 branchStr = ''' 130 NextThumb = !Thumb; 131 NPC = %(newPC)s; 132 ''' 133 br_tgt_code = '''pcs.nextThumb(!branchPC.thumb());\n''' + \ 134 br_tgt_code 135 else: 136 branchStr = "IWNPC = %(newPC)s;" 137 branchStr = branchStr % { "newPC" : newPC } 138 139 code = blxCode % {"link": linkStr, 140 "newPC": newPC, 141 "branch": branchStr} 142 blxIop = InstObjParams(mnem, Name, base, 143 {"code": code, "brTgtCode" : br_tgt_code, 144 "predicate_test": predicateTest}, instFlags) 145 header_output += declare.subst(blxIop) 146 decoder_output += constructor.subst(blxIop) 147 exec_output += PredOpExecute.subst(blxIop) 148 if imm: 149 decoder_output += BranchTarget.subst(blxIop) 150 151 #Ignore BXJ for now 152 153 #CBNZ, CBZ. These are always unconditional as far as predicates 154 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): 155 code = 'NPC = (uint32_t)(PC + imm);\n' 156 predTest = "Op1 %(test)s 0" % {"test": test} 157 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", 158 {"code": code, "predicate_test": predTest}, 159 ["IsIndirectControl"]) 160 header_output += BranchImmRegDeclare.subst(iop) 161 decoder_output += BranchImmRegConstructor.subst(iop) 162 exec_output += PredOpExecute.subst(iop) 163 164 #TBB, TBH 165 for isTbh in (0, 1): 166 if isTbh: 167 eaCode = ''' 168 unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned | 169 ArmISA::TLB::AlignHalfWord | 170 ArmISA::TLB::MustBeOne; 171 EA = Op1 + Op2 * 2 172 ''' 173 accCode = 'NPC = PC + 2 * (Mem.uh);\n' 174 mnem = "tbh" 175 else: 176 eaCode = ''' 177 unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned | 178 ArmISA::TLB::AlignByte | 179 ArmISA::TLB::MustBeOne; 180 EA = Op1 + Op2 181 ''' 182 accCode = 'NPC = PC + 2 * (Mem.ub)' 183 mnem = "tbb" 184 iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg", 185 {'ea_code': eaCode, 186 'memacc_code': accCode, 187 'predicate_test': predicateTest}, 188 ["IsIndirectControl"]) 189 header_output += BranchTableDeclare.subst(iop) 190 decoder_output += BranchRegRegConstructor.subst(iop) 191 exec_output += LoadExecute.subst(iop) + \ 192 LoadInitiateAcc.subst(iop) + \ 193 LoadCompleteAcc.subst(iop) 194}}; 195