branch.isa revision 7594
17151Sgblack@eecs.umich.edu// -*- mode:c++ -*-
27151Sgblack@eecs.umich.edu
37151Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited
47151Sgblack@eecs.umich.edu// All rights reserved
57151Sgblack@eecs.umich.edu//
67151Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77151Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87151Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97151Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107151Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117151Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127151Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137151Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147151Sgblack@eecs.umich.edu//
157151Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
167151Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
177151Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
187151Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
197151Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
207151Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
217151Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
227151Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
237151Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
247151Sgblack@eecs.umich.edu// this software without specific prior written permission.
257151Sgblack@eecs.umich.edu//
267151Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
277151Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
287151Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
297151Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
307151Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
317151Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
327151Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
337151Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
347151Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
357151Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
367151Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
377151Sgblack@eecs.umich.edu//
387151Sgblack@eecs.umich.edu// Authors: Gabe Black
397151Sgblack@eecs.umich.edu
407151Sgblack@eecs.umich.edulet {{
417151Sgblack@eecs.umich.edu
427151Sgblack@eecs.umich.edu    header_output = ""
437151Sgblack@eecs.umich.edu    decoder_output = ""
447151Sgblack@eecs.umich.edu    exec_output = ""
457151Sgblack@eecs.umich.edu
467151Sgblack@eecs.umich.edu    # B, BL
477151Sgblack@eecs.umich.edu    for (mnem, link) in (("b", False), ("bl", True)):
487151Sgblack@eecs.umich.edu        bCode = '''
497594SGene.Wu@arm.com        Addr curPc = readPC(xc);
507594SGene.Wu@arm.com        NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32));
517151Sgblack@eecs.umich.edu        '''
527151Sgblack@eecs.umich.edu        if (link):
537151Sgblack@eecs.umich.edu            bCode += '''
547594SGene.Wu@arm.com                Addr tBit = curPc & (ULL(1) << PcTBitShift);
557151Sgblack@eecs.umich.edu                if (!tBit)
567594SGene.Wu@arm.com                    LR = curPc - 4;
577151Sgblack@eecs.umich.edu                else
587594SGene.Wu@arm.com                    LR = curPc | 1;
597151Sgblack@eecs.umich.edu            '''
607151Sgblack@eecs.umich.edu
617151Sgblack@eecs.umich.edu        bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
627151Sgblack@eecs.umich.edu                             {"code": bCode,
637151Sgblack@eecs.umich.edu                              "predicate_test": predicateTest})
647151Sgblack@eecs.umich.edu        header_output += BranchImmCondDeclare.subst(bIop)
657151Sgblack@eecs.umich.edu        decoder_output += BranchImmCondConstructor.subst(bIop)
667151Sgblack@eecs.umich.edu        exec_output += PredOpExecute.subst(bIop)
677151Sgblack@eecs.umich.edu
687151Sgblack@eecs.umich.edu    # BX, BLX
697151Sgblack@eecs.umich.edu    blxCode = '''
707594SGene.Wu@arm.com    Addr curPc = readPC(xc);
717594SGene.Wu@arm.com    Addr tBit = curPc & (ULL(1) << PcTBitShift);
727151Sgblack@eecs.umich.edu    bool arm = !tBit;
737151Sgblack@eecs.umich.edu    arm = arm; // In case it's not used otherwise.
747151Sgblack@eecs.umich.edu    %(link)s
757151Sgblack@eecs.umich.edu    // Switch modes
767151Sgblack@eecs.umich.edu    %(branch)s
777151Sgblack@eecs.umich.edu    '''
787151Sgblack@eecs.umich.edu
797151Sgblack@eecs.umich.edu    blxList = (("blx", True, True),
807151Sgblack@eecs.umich.edu               ("blx", False, True),
817151Sgblack@eecs.umich.edu               ("bx", False, False))
827151Sgblack@eecs.umich.edu
837151Sgblack@eecs.umich.edu    for (mnem, imm, link) in blxList:
847151Sgblack@eecs.umich.edu        Name = mnem.capitalize()
857151Sgblack@eecs.umich.edu        if imm:
867151Sgblack@eecs.umich.edu            Name += "Imm"
877151Sgblack@eecs.umich.edu            # Since we're switching ISAs, the target ISA will be the opposite
887151Sgblack@eecs.umich.edu            # of the current ISA. !arm is whether the target is ARM.
897594SGene.Wu@arm.com            newPC = '(!arm ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
907151Sgblack@eecs.umich.edu            base = "BranchImm"
917151Sgblack@eecs.umich.edu            declare = BranchImmDeclare
927151Sgblack@eecs.umich.edu            constructor = BranchImmConstructor
937151Sgblack@eecs.umich.edu        else:
947151Sgblack@eecs.umich.edu            Name += "Reg"
957282Sgblack@eecs.umich.edu            newPC = 'Op1'
967151Sgblack@eecs.umich.edu            base = "BranchRegCond"
977151Sgblack@eecs.umich.edu            declare = BranchRegCondDeclare
987151Sgblack@eecs.umich.edu            constructor = BranchRegCondConstructor
997151Sgblack@eecs.umich.edu        if link and imm:
1007151Sgblack@eecs.umich.edu            linkStr = '''
1017151Sgblack@eecs.umich.edu                // The immediate version of the blx thumb instruction
1027151Sgblack@eecs.umich.edu                // is 32 bits wide, but "next pc" doesn't reflect that
1037151Sgblack@eecs.umich.edu                // so we don't want to substract 2 from it at this point
1047151Sgblack@eecs.umich.edu                if (arm)
1057594SGene.Wu@arm.com                    LR = curPc - 4;
1067151Sgblack@eecs.umich.edu                else
1077594SGene.Wu@arm.com                    LR = curPc  | 1;
1087151Sgblack@eecs.umich.edu            '''
1097151Sgblack@eecs.umich.edu        elif link:
1107151Sgblack@eecs.umich.edu            linkStr = '''
1117151Sgblack@eecs.umich.edu                if (arm)
1127594SGene.Wu@arm.com                    LR = curPc - 4;
1137151Sgblack@eecs.umich.edu                else
1147594SGene.Wu@arm.com                    LR = (curPc - 2) | 1;
1157151Sgblack@eecs.umich.edu            '''
1167151Sgblack@eecs.umich.edu        else:
1177151Sgblack@eecs.umich.edu            linkStr = ""
1187282Sgblack@eecs.umich.edu
1197282Sgblack@eecs.umich.edu        if imm and link: #blx with imm
1207282Sgblack@eecs.umich.edu            branchStr = '''
1217594SGene.Wu@arm.com                Addr tempPc = ((%(newPC)s) & mask(32)) | (curPc & ~mask(32));
1227282Sgblack@eecs.umich.edu                FNPC = tempPc ^ (ULL(1) << PcTBitShift);
1237282Sgblack@eecs.umich.edu            '''
1247282Sgblack@eecs.umich.edu        else:
1257282Sgblack@eecs.umich.edu            branchStr = "IWNPC = %(newPC)s;"
1267282Sgblack@eecs.umich.edu        branchStr = branchStr % { "newPC" : newPC }
1277282Sgblack@eecs.umich.edu
1287151Sgblack@eecs.umich.edu        code = blxCode % {"link": linkStr,
1297151Sgblack@eecs.umich.edu                          "newPC": newPC,
1307151Sgblack@eecs.umich.edu                          "branch": branchStr}
1317151Sgblack@eecs.umich.edu        blxIop = InstObjParams(mnem, Name, base,
1327151Sgblack@eecs.umich.edu                               {"code": code,
1337151Sgblack@eecs.umich.edu                                "predicate_test": predicateTest})
1347151Sgblack@eecs.umich.edu        header_output += declare.subst(blxIop)
1357151Sgblack@eecs.umich.edu        decoder_output += constructor.subst(blxIop)
1367151Sgblack@eecs.umich.edu        exec_output += PredOpExecute.subst(blxIop)
1377151Sgblack@eecs.umich.edu
1387151Sgblack@eecs.umich.edu    #Ignore BXJ for now
1397151Sgblack@eecs.umich.edu
1407151Sgblack@eecs.umich.edu    #CBNZ, CBZ. These are always unconditional as far as predicates
1417151Sgblack@eecs.umich.edu    for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
1427151Sgblack@eecs.umich.edu        code = '''
1437594SGene.Wu@arm.com        Addr curPc = readPC(xc);
1447594SGene.Wu@arm.com        NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32));
1457151Sgblack@eecs.umich.edu        '''
1467151Sgblack@eecs.umich.edu        predTest = "Op1 %(test)s 0" % {"test": test}
1477151Sgblack@eecs.umich.edu        iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
1487151Sgblack@eecs.umich.edu                            {"code": code, "predicate_test": predTest})
1497151Sgblack@eecs.umich.edu        header_output += BranchImmRegDeclare.subst(iop)
1507151Sgblack@eecs.umich.edu        decoder_output += BranchImmRegConstructor.subst(iop)
1517151Sgblack@eecs.umich.edu        exec_output += PredOpExecute.subst(iop)
1527151Sgblack@eecs.umich.edu
1537151Sgblack@eecs.umich.edu    #TBB, TBH
1547151Sgblack@eecs.umich.edu    for isTbh in (0, 1):
1557151Sgblack@eecs.umich.edu        if isTbh:
1567294Sgblack@eecs.umich.edu            eaCode = '''
1577294Sgblack@eecs.umich.edu            unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
1587294Sgblack@eecs.umich.edu                                      ArmISA::TLB::AlignHalfWord |
1597294Sgblack@eecs.umich.edu                                      ArmISA::TLB::MustBeOne;
1607294Sgblack@eecs.umich.edu            EA = Op1 + Op2 * 2
1617294Sgblack@eecs.umich.edu            '''
1627151Sgblack@eecs.umich.edu            accCode = "NPC = readPC(xc) + 2 * (Mem.uh);"
1637151Sgblack@eecs.umich.edu            mnem = "tbh"
1647151Sgblack@eecs.umich.edu        else:
1657294Sgblack@eecs.umich.edu            eaCode = '''
1667294Sgblack@eecs.umich.edu            unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
1677294Sgblack@eecs.umich.edu                                      ArmISA::TLB::AlignByte |
1687294Sgblack@eecs.umich.edu                                      ArmISA::TLB::MustBeOne;
1697294Sgblack@eecs.umich.edu            EA = Op1 + Op2
1707294Sgblack@eecs.umich.edu            '''
1717151Sgblack@eecs.umich.edu            accCode = "NPC = readPC(xc) + 2 * (Mem.ub);"
1727151Sgblack@eecs.umich.edu            mnem = "tbb"
1737151Sgblack@eecs.umich.edu        iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
1747151Sgblack@eecs.umich.edu                            {'ea_code': eaCode,
1757151Sgblack@eecs.umich.edu                             'memacc_code': accCode,
1767151Sgblack@eecs.umich.edu                             'predicate_test': predicateTest})
1777151Sgblack@eecs.umich.edu        header_output += BranchTableDeclare.subst(iop)
1787151Sgblack@eecs.umich.edu        decoder_output += BranchRegRegConstructor.subst(iop)
1797151Sgblack@eecs.umich.edu        exec_output += LoadExecute.subst(iop) + \
1807151Sgblack@eecs.umich.edu                       LoadInitiateAcc.subst(iop) + \
1817151Sgblack@eecs.umich.edu                       LoadCompleteAcc.subst(iop)
1827151Sgblack@eecs.umich.edu}};
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