xref: /gem5/src/arch/arm/isa/insts/branch.isa

// -*- mode:c++ -*-

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// Authors: Gabe Black

let {{

    header_output = ""
    decoder_output = ""
    exec_output = ""

    # B, BL
    for (mnem, link) in (("b", False), ("bl", True)):
        bCode = '''
        Addr PC = readPC(xc);
        NPC = ((PC + imm) & mask(32)) | (PC & ~mask(32));
        '''
        if (link):
            bCode += '''
                Addr tBit = PC & (ULL(1) << PcTBitShift);
                if (!tBit)
                    LR = PC - 4;
                else
                    LR = PC | 1;
            '''

        bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
                             {"code": bCode,
                              "predicate_test": predicateTest})
        header_output += BranchImmCondDeclare.subst(bIop)
        decoder_output += BranchImmCondConstructor.subst(bIop)
        exec_output += PredOpExecute.subst(bIop)

    # BX, BLX
    blxCode = '''
    Addr PC = readPC(xc);
    Addr tBit = PC & (ULL(1) << PcTBitShift);
    bool arm = !tBit;
    arm = arm; // In case it's not used otherwise.
    %(link)s
    // Switch modes
    %(branch)s
    '''

    blxList = (("blx", True, True),
               ("blx", False, True),
               ("bx", False, False))

    for (mnem, imm, link) in blxList:
        Name = mnem.capitalize()
        if imm:
            Name += "Imm"
            # Since we're switching ISAs, the target ISA will be the opposite
            # of the current ISA. !arm is whether the target is ARM.
            newPC = '(!arm ? (roundDown(PC, 4) + imm) : (PC + imm))'
            base = "BranchImm"
            declare = BranchImmDeclare
            constructor = BranchImmConstructor
        else:
            Name += "Reg"
            newPC = 'Op1'
            base = "BranchRegCond"
            declare = BranchRegCondDeclare
            constructor = BranchRegCondConstructor
        if link and imm:
            linkStr = '''
                // The immediate version of the blx thumb instruction
                // is 32 bits wide, but "next pc" doesn't reflect that
                // so we don't want to substract 2 from it at this point
                if (arm)
                    LR = PC - 4;
                else
                    LR = PC  | 1;
            '''
        elif link:
            linkStr = '''
                if (arm)
                    LR = PC - 4;
                else
                    LR = (PC - 2) | 1;
            '''
        else:
            linkStr = ""

        if imm and link: #blx with imm
            branchStr = '''
                Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
                FNPC = tempPc ^ (ULL(1) << PcTBitShift);
            '''
        else:
            branchStr = "IWNPC = %(newPC)s;"
        branchStr = branchStr % { "newPC" : newPC }

        code = blxCode % {"link": linkStr,
                          "newPC": newPC,
                          "branch": branchStr}
        blxIop = InstObjParams(mnem, Name, base,
                               {"code": code,
                                "predicate_test": predicateTest})
        header_output += declare.subst(blxIop)
        decoder_output += constructor.subst(blxIop)
        exec_output += PredOpExecute.subst(blxIop)

    #Ignore BXJ for now

    #CBNZ, CBZ. These are always unconditional as far as predicates
    for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
        code = '''
        Addr PC = readPC(xc);
        NPC = ((PC + imm) & mask(32)) | (PC & ~mask(32));
        '''
        predTest = "Op1 %(test)s 0" % {"test": test}
        iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
                            {"code": code, "predicate_test": predTest})
        header_output += BranchImmRegDeclare.subst(iop)
        decoder_output += BranchImmRegConstructor.subst(iop)
        exec_output += PredOpExecute.subst(iop)

    #TBB, TBH
    for isTbh in (0, 1):
        if isTbh:
            eaCode = '''
            unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
                                      ArmISA::TLB::AlignHalfWord |
                                      ArmISA::TLB::MustBeOne;
            EA = Op1 + Op2 * 2
            '''
            accCode = "NPC = readPC(xc) + 2 * (Mem.uh);"
            mnem = "tbh"
        else:
            eaCode = '''
            unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
                                      ArmISA::TLB::AlignByte |
                                      ArmISA::TLB::MustBeOne;
            EA = Op1 + Op2
            '''
            accCode = "NPC = readPC(xc) + 2 * (Mem.ub);"
            mnem = "tbb"
        iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
                            {'ea_code': eaCode,
                             'memacc_code': accCode,
                             'predicate_test': predicateTest})
        header_output += BranchTableDeclare.subst(iop)
        decoder_output += BranchRegRegConstructor.subst(iop)
        exec_output += LoadExecute.subst(iop) + \
                       LoadInitiateAcc.subst(iop) + \
                       LoadCompleteAcc.subst(iop)
}};