includes.isa revision 11165
12SN/A// -*- mode:c++ -*- 28733Sgeoffrey.blake@arm.com 37338SAli.Saidi@ARM.com// Copyright (c) 2010, 2012 ARM Limited 47338SAli.Saidi@ARM.com// All rights reserved 57338SAli.Saidi@ARM.com// 67338SAli.Saidi@ARM.com// The license below extends only to copyright in the software and shall 77338SAli.Saidi@ARM.com// not be construed as granting a license to any other intellectual 87338SAli.Saidi@ARM.com// property including but not limited to intellectual property relating 97338SAli.Saidi@ARM.com// to a hardware implementation of the functionality of the software 107338SAli.Saidi@ARM.com// licensed hereunder. You may use the software subject to the license 117338SAli.Saidi@ARM.com// terms below provided that you ensure that this notice is replicated 127338SAli.Saidi@ARM.com// unmodified and in its entirety in all distributions of the software, 137338SAli.Saidi@ARM.com// modified or unmodified, in source code or in binary form. 141762SN/A// 152SN/A// Copyright (c) 2007-2008 The Florida State University 162SN/A// All rights reserved. 172SN/A// 182SN/A// Redistribution and use in source and binary forms, with or without 192SN/A// modification, are permitted provided that the following conditions are 202SN/A// met: redistributions of source code must retain the above copyright 212SN/A// notice, this list of conditions and the following disclaimer; 222SN/A// redistributions in binary form must reproduce the above copyright 232SN/A// notice, this list of conditions and the following disclaimer in the 242SN/A// documentation and/or other materials provided with the distribution; 252SN/A// neither the name of the copyright holders nor the names of its 262SN/A// contributors may be used to endorse or promote products derived from 272SN/A// this software without specific prior written permission. 282SN/A// 292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu// 412SN/A// Authors: Stephen Hines 422SN/A 438779Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 448779Sgblack@eecs.umich.edu// 458779Sgblack@eecs.umich.edu// Output include file directives. 462439SN/A// 478779Sgblack@eecs.umich.edu 488229Snate@binkert.orgoutput header {{ 496216Snate@binkert.org#include <iostream> 50146SN/A#include <sstream> 51146SN/A 52146SN/A#include "arch/arm/insts/branch.hh" 53146SN/A#include "arch/arm/insts/branch64.hh" 54146SN/A#include "arch/arm/insts/data64.hh" 556216Snate@binkert.org#include "arch/arm/insts/fplib.hh" 566658Snate@binkert.org#include "arch/arm/insts/macromem.hh" 578229Snate@binkert.org#include "arch/arm/insts/mem.hh" 581717SN/A#include "arch/arm/insts/mem64.hh" 598887Sgeoffrey.blake@arm.com#include "arch/arm/insts/misc.hh" 608887Sgeoffrey.blake@arm.com#include "arch/arm/insts/misc64.hh" 61146SN/A#include "arch/arm/insts/mult.hh" 621977SN/A#include "arch/arm/insts/neon64_mem.hh" 632683Sktlim@umich.edu#include "arch/arm/insts/pred_inst.hh" 641717SN/A#include "arch/arm/insts/pseudo.hh" 65146SN/A#include "arch/arm/insts/static_inst.hh" 662683Sktlim@umich.edu#include "arch/arm/insts/vfp.hh" 678232Snate@binkert.org#include "arch/arm/isa_traits.hh" 688232Snate@binkert.org#include "mem/packet.hh" 698232Snate@binkert.org#include "sim/faults.hh" 708779Sgblack@eecs.umich.edu#include "enums/DecoderFlavour.hh" 713348Sbinkertn@umich.edu}}; 726105Ssteve.reinhardt@amd.com 736216Snate@binkert.orgoutput decoder {{ 742036SN/A#include <string> 75146SN/A#include "arch/arm/decoder.hh" 768817Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 778793Sgblack@eecs.umich.edu#include "arch/arm/intregs.hh" 7856SN/A#include "arch/arm/isa_traits.hh" 7956SN/A#include "arch/arm/utility.hh" 80695SN/A#include "base/loader/symtab.hh" 812901Ssaidi@eecs.umich.edu#include "base/cprintf.hh" 822SN/A#include "cpu/thread_context.hh" 832SN/A 842449SN/Ausing namespace ArmISA; 851355SN/A}}; 865529Snate@binkert.org 879023Sgblack@eecs.umich.eduoutput exec {{ 88224SN/A#include <cmath> 898793Sgblack@eecs.umich.edu 909384SAndreas.Sandberg@arm.com#include "arch/arm/faults.hh" 919384SAndreas.Sandberg@arm.com#include "arch/arm/isa_traits.hh" 928793Sgblack@eecs.umich.edu#include "arch/arm/utility.hh" 938820Sgblack@eecs.umich.edu#include "arch/generic/memhelpers.hh" 949384SAndreas.Sandberg@arm.com#include "base/condcodes.hh" 952SN/A#include "cpu/base.hh" 966029Ssteve.reinhardt@amd.com#include "sim/pseudo_inst.hh" 972672Sktlim@umich.edu#if defined(linux) 982683Sktlim@umich.edu#include <fenv.h> 992SN/A#endif 1008733Sgeoffrey.blake@arm.com 1018733Sgeoffrey.blake@arm.com#include "base/cp_annotate.hh" 1028733Sgeoffrey.blake@arm.com#include "debug/Arm.hh" 1038733Sgeoffrey.blake@arm.com#include "mem/packet.hh" 1048733Sgeoffrey.blake@arm.com#include "mem/packet_access.hh" 1058733Sgeoffrey.blake@arm.com#include "sim/sim_exit.hh" 1068733Sgeoffrey.blake@arm.com 1078733Sgeoffrey.blake@arm.comusing namespace ArmISA; 1088733Sgeoffrey.blake@arm.com 1098733Sgeoffrey.blake@arm.com}}; 1108733Sgeoffrey.blake@arm.com 1112SN/A