uncond.isa revision 7435:62bdb68bb314
1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Gabe Black 37 38def format ArmUnconditional() {{ 39 decode_block = ''' 40 { 41 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 42 const uint32_t op1 = bits(machInst, 27, 20); 43 if (bits(op1, 7) == 0) { 44 const uint32_t op2 = bits(machInst, 7, 4); 45 if (op1 == 0x10) { 46 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) { 47 return new Setend(machInst, bits(machInst, 9)); 48 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) { 49 const bool enable = bits(machInst, 19, 18) == 0x2; 50 const uint32_t mods = bits(machInst, 4, 0) | 51 (bits(machInst, 8, 6) << 5) | 52 (bits(machInst, 17) << 8) | 53 ((enable ? 1 : 0) << 9); 54 return new Cps(machInst, mods); 55 } 56 } else if (bits(op1, 6, 5) == 0x1) { 57 return decodeNeonData(machInst); 58 } else if (bits(op1, 6, 4) == 0x4) { 59 if (bits(op1, 0) == 0) { 60 return decodeNeonMem(machInst); 61 } else if (bits(op1, 2, 0) == 1) { 62 // Unallocated memory hint 63 return new NopInst(machInst); 64 } else if (bits(op1, 2, 0) == 5) { 65 const bool add = bits(machInst, 23); 66 const uint32_t imm12 = bits(machInst, 11, 0); 67 if (add) { 68 return new %(pli_iadd)s(machInst, INTREG_ZERO, 69 rn, add, imm12); 70 } else { 71 return new %(pli_isub)s(machInst, INTREG_ZERO, 72 rn, add, imm12); 73 } 74 } 75 } else if (bits(op1, 6, 4) == 0x5) { 76 if (bits(op1, 1, 0) == 0x1) { 77 const bool add = bits(machInst, 23); 78 const bool pldw = bits(machInst, 22); 79 const uint32_t imm12 = bits(machInst, 11, 0); 80 if (pldw) { 81 if (add) { 82 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 83 rn, add, imm12); 84 } else { 85 return new %(pldw_isub)s(machInst, INTREG_ZERO, 86 rn, add, imm12); 87 } 88 } else { 89 if (add) { 90 return new %(pld_iadd)s(machInst, INTREG_ZERO, 91 rn, add, imm12); 92 } else { 93 return new %(pld_isub)s(machInst, INTREG_ZERO, 94 rn, add, imm12); 95 } 96 } 97 } else if (op1 == 0x57) { 98 switch (op2) { 99 case 0x1: 100 return new WarnUnimplemented("clrex", machInst); 101 case 0x4: 102 return new WarnUnimplemented("dsb", machInst); 103 case 0x5: 104 return new WarnUnimplemented("dmb", machInst); 105 case 0x6: 106 return new WarnUnimplemented("isb", machInst); 107 } 108 } 109 } else if (bits(op2, 0) == 0) { 110 switch (op1 & 0xf7) { 111 case 0x61: 112 // Unallocated memory hint 113 return new NopInst(machInst); 114 case 0x65: 115 { 116 const uint32_t imm5 = bits(machInst, 11, 7); 117 const uint32_t type = bits(machInst, 6, 5); 118 const bool add = bits(machInst, 23); 119 const IntRegIndex rm = 120 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 121 if (add) { 122 return new %(pli_radd)s(machInst, INTREG_ZERO, rn, 123 add, imm5, type, rm); 124 } else { 125 return new %(pli_rsub)s(machInst, INTREG_ZERO, rn, 126 add, imm5, type, rm); 127 } 128 } 129 case 0x71: 130 case 0x75: 131 { 132 const uint32_t imm5 = bits(machInst, 11, 7); 133 const uint32_t type = bits(machInst, 6, 5); 134 const bool add = bits(machInst, 23); 135 const bool pldw = bits(machInst, 22); 136 const IntRegIndex rm = 137 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 138 if (pldw) { 139 if (add) { 140 return new %(pldw_radd)s(machInst, INTREG_ZERO, 141 rn, add, imm5, 142 type, rm); 143 } else { 144 return new %(pldw_rsub)s(machInst, INTREG_ZERO, 145 rn, add, imm5, 146 type, rm); 147 } 148 } else { 149 if (add) { 150 return new %(pld_radd)s(machInst, INTREG_ZERO, 151 rn, add, imm5, 152 type, rm); 153 } else { 154 return new %(pld_rsub)s(machInst, INTREG_ZERO, 155 rn, add, imm5, 156 type, rm); 157 } 158 } 159 } 160 } 161 } 162 } else { 163 switch (bits(machInst, 26, 25)) { 164 case 0x0: 165 { 166 const uint32_t val = ((machInst >> 20) & 0x5); 167 if (val == 0x4) { 168 const uint32_t mode = bits(machInst, 4, 0); 169 switch (bits(machInst, 24, 21)) { 170 case 0x2: 171 return new %(srs)s(machInst, mode, 172 SrsOp::DecrementAfter, false); 173 case 0x3: 174 return new %(srs_w)s(machInst, mode, 175 SrsOp::DecrementAfter, true); 176 case 0x6: 177 return new %(srs_u)s(machInst, mode, 178 SrsOp::IncrementAfter, false); 179 case 0x7: 180 return new %(srs_uw)s(machInst, mode, 181 SrsOp::IncrementAfter, true); 182 case 0xa: 183 return new %(srs_p)s(machInst, mode, 184 SrsOp::DecrementBefore, false); 185 case 0xb: 186 return new %(srs_pw)s(machInst, mode, 187 SrsOp::DecrementBefore, true); 188 case 0xe: 189 return new %(srs_pu)s(machInst, mode, 190 SrsOp::IncrementBefore, false); 191 case 0xf: 192 return new %(srs_puw)s(machInst, mode, 193 SrsOp::IncrementBefore, true); 194 } 195 return new Unknown(machInst); 196 } else if (val == 0x1) { 197 switch (bits(machInst, 24, 21)) { 198 case 0x0: 199 return new %(rfe)s(machInst, rn, 200 RfeOp::DecrementAfter, false); 201 case 0x1: 202 return new %(rfe_w)s(machInst, rn, 203 RfeOp::DecrementAfter, true); 204 case 0x4: 205 return new %(rfe_u)s(machInst, rn, 206 RfeOp::IncrementAfter, false); 207 case 0x5: 208 return new %(rfe_uw)s(machInst, rn, 209 RfeOp::IncrementAfter, true); 210 case 0x8: 211 return new %(rfe_p)s(machInst, rn, 212 RfeOp::DecrementBefore, false); 213 case 0x9: 214 return new %(rfe_pw)s(machInst, rn, 215 RfeOp::DecrementBefore, true); 216 case 0xc: 217 return new %(rfe_pu)s(machInst, rn, 218 RfeOp::IncrementBefore, false); 219 case 0xd: 220 return new %(rfe_puw)s(machInst, rn, 221 RfeOp::IncrementBefore, true); 222 } 223 return new Unknown(machInst); 224 } 225 } 226 break; 227 case 0x1: 228 { 229 const uint32_t imm = 230 (sext<26>(bits(machInst, 23, 0) << 2)) | 231 (bits(machInst, 24) << 1); 232 return new BlxImm(machInst, imm); 233 } 234 case 0x2: 235 if (bits(op1, 4, 0) != 0) { 236 if (CPNUM == 0xa || CPNUM == 0xb) { 237 return decodeExtensionRegLoadStore(machInst); 238 } 239 if (bits(op1, 0) == 1) { 240 if (rn == INTREG_PC) { 241 if (bits(op1, 4, 3) != 0x0) { 242 return new WarnUnimplemented( 243 "ldc, ldc2 (literal)", machInst); 244 } 245 } else { 246 if (op1 == 0xC3 || op1 == 0xC7) { 247 return new WarnUnimplemented( 248 "ldc, ldc2 (immediate)", machInst); 249 } 250 } 251 if (op1 == 0xC5) { 252 return new WarnUnimplemented( 253 "mrrc, mrrc2", machInst); 254 } 255 } else { 256 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) { 257 return new WarnUnimplemented( 258 "stc, stc2", machInst); 259 } else if (op1 == 0xC4) { 260 return new WarnUnimplemented( 261 "mcrr, mcrrc", machInst); 262 } 263 } 264 } 265 break; 266 case 0x3: 267 if (bits(op1, 4) == 0) { 268 if (CPNUM == 0xa || CPNUM == 0xb) { 269 return decodeShortFpTransfer(machInst); 270 } else if (CPNUM == 0xf) { 271 return decodeMcrMrc15(machInst); 272 } 273 const bool op = bits(machInst, 4); 274 if (op) { 275 if (bits(op1, 0)) { 276 return new WarnUnimplemented( 277 "mrc, mrc2", machInst); 278 } else { 279 return new WarnUnimplemented( 280 "mcr, mcr2", machInst); 281 } 282 } else { 283 return new WarnUnimplemented("cdp, cdp2", machInst); 284 } 285 } 286 break; 287 } 288 } 289 return new Unknown(machInst); 290 } 291 ''' % { 292 "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1), 293 "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1), 294 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1), 295 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 296 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 297 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 298 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 299 "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1), 300 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 301 "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1), 302 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 303 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1), 304 "rfe" : "RFE_" + loadImmClassName(True, False, False, 8), 305 "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8), 306 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 307 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8), 308 "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8), 309 "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8), 310 "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8), 311 "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8), 312 "srs" : "SRS_" + storeImmClassName(True, False, False, 8), 313 "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8), 314 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8), 315 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8), 316 "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8), 317 "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8), 318 "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8), 319 "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8) 320 }; 321}}; 322