uncond.isa revision 7316:bb190cb8ee69 
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39    decode_block = '''
40    {
41        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42        const uint32_t op1 = bits(machInst, 27, 20);
43        if (bits(op1, 7) == 0) {
44            const uint32_t op2 = bits(machInst, 7, 4);
45            if (op1 == 0x10) {
46                if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47                    return new Setend(machInst, bits(machInst, 9));
48                } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49                    const bool enable = bits(machInst, 19, 18) == 0x2;
50                    const uint32_t mods = bits(machInst, 4, 0) |
51                                          (bits(machInst, 8, 6) << 5) |
52                                          (bits(machInst, 17) << 8) |
53                                          ((enable ? 1 : 0) << 9);
54                    return new Cps(machInst, mods);
55                }
56            } else if (bits(op1, 6, 5) == 0x1) {
57                return new WarnUnimplemented(
58                        "Advanced SIMD data-processing", machInst);
59            } else if (bits(op1, 6, 4) == 0x4) {
60                if (bits(op1, 0) == 0) {
61                    return new WarnUnimplemented(
62                            "Advanced SIMD element or structure load/store",
63                            machInst);
64                } else if (bits(op1, 2, 0) == 1) {
65                    // Unallocated memory hint
66                    return new NopInst(machInst);
67                } else if (bits(op1, 2, 0) == 5) {
68                    const bool add = bits(machInst, 23);
69                    const uint32_t imm12 = bits(machInst, 11, 0);
70                    if (add) {
71                        return new %(pli_iadd)s(machInst, INTREG_ZERO,
72                                                rn, add, imm12);
73                    } else {
74                        return new %(pli_isub)s(machInst, INTREG_ZERO,
75                                                rn, add, imm12);
76                    }
77                }
78            } else if (bits(op1, 6, 4) == 0x5) {
79                if (bits(op1, 1, 0) == 0x1) {
80                    const bool add = bits(machInst, 23);
81                    const bool pldw = bits(machInst, 22);
82                    const uint32_t imm12 = bits(machInst, 11, 0);
83                    if (pldw) {
84                        if (add) {
85                            return new %(pldw_iadd)s(machInst, INTREG_ZERO,
86                                                     rn, add, imm12);
87                        } else {
88                            return new %(pldw_isub)s(machInst, INTREG_ZERO,
89                                                     rn, add, imm12);
90                        }
91                    } else {
92                        if (add) {
93                            return new %(pld_iadd)s(machInst, INTREG_ZERO,
94                                                    rn, add, imm12);
95                        } else {
96                            return new %(pld_isub)s(machInst, INTREG_ZERO,
97                                                    rn, add, imm12);
98                        }
99                    }
100                } else if (op1 == 0x57) {
101                    switch (op2) {
102                      case 0x1:
103                        return new WarnUnimplemented("clrex", machInst);
104                      case 0x4:
105                        return new WarnUnimplemented("dsb", machInst);
106                      case 0x5:
107                        return new WarnUnimplemented("dmb", machInst);
108                      case 0x6:
109                        return new WarnUnimplemented("isb", machInst);
110                    }
111                }
112            } else if (bits(op2, 0) == 0) {
113                switch (op1 & 0xf7) {
114                  case 0x61:
115                    // Unallocated memory hint
116                    return new NopInst(machInst);
117                  case 0x65:
118                    {
119                        const uint32_t imm5 = bits(machInst, 11, 7);
120                        const uint32_t type = bits(machInst, 6, 5);
121                        const bool add = bits(machInst, 23);
122                        const IntRegIndex rm =
123                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
124                        if (add) {
125                            return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
126                                                    add, imm5, type, rm);
127                        } else {
128                            return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
129                                                    add, imm5, type, rm);
130                        }
131                    }
132                  case 0x71:
133                  case 0x75:
134                    {
135                        const uint32_t imm5 = bits(machInst, 11, 7);
136                        const uint32_t type = bits(machInst, 6, 5);
137                        const bool add = bits(machInst, 23);
138                        const bool pldw = bits(machInst, 22);
139                        const IntRegIndex rm =
140                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
141                        if (pldw) {
142                            if (add) {
143                                return new %(pldw_radd)s(machInst, INTREG_ZERO,
144                                                         rn, add, imm5,
145                                                         type, rm);
146                            } else {
147                                return new %(pldw_rsub)s(machInst, INTREG_ZERO,
148                                                         rn, add, imm5,
149                                                         type, rm);
150                            }
151                        } else {
152                            if (add) {
153                                return new %(pld_radd)s(machInst, INTREG_ZERO,
154                                                        rn, add, imm5,
155                                                        type, rm);
156                            } else {
157                                return new %(pld_rsub)s(machInst, INTREG_ZERO,
158                                                        rn, add, imm5,
159                                                        type, rm);
160                            }
161                        }
162                    }
163                }
164            }
165        } else {
166            switch (bits(machInst, 26, 25)) {
167              case 0x0:
168                {
169                    const uint32_t val = ((machInst >> 20) & 0x5);
170                    if (val == 0x4) {
171                        const uint32_t mode = bits(machInst, 4, 0);
172                        switch (bits(machInst, 24, 21)) {
173                          case 0x2:
174                            return new %(srs)s(machInst, mode,
175                                    SrsOp::DecrementAfter, false);
176                          case 0x3:
177                            return new %(srs_w)s(machInst, mode,
178                                    SrsOp::DecrementAfter, true);
179                          case 0x6:
180                            return new %(srs_u)s(machInst, mode,
181                                    SrsOp::IncrementAfter, false);
182                          case 0x7:
183                            return new %(srs_uw)s(machInst, mode,
184                                    SrsOp::IncrementAfter, true);
185                          case 0xa:
186                            return new %(srs_p)s(machInst, mode,
187                                    SrsOp::DecrementBefore, false);
188                          case 0xb:
189                            return new %(srs_pw)s(machInst, mode,
190                                    SrsOp::DecrementBefore, true);
191                          case 0xe:
192                            return new %(srs_pu)s(machInst, mode,
193                                    SrsOp::IncrementBefore, false);
194                          case 0xf:
195                            return new %(srs_puw)s(machInst, mode,
196                                    SrsOp::IncrementBefore, true);
197                        }
198                        return new Unknown(machInst);
199                    } else if (val == 0x1) {
200                        switch (bits(machInst, 24, 21)) {
201                          case 0x0:
202                            return new %(rfe)s(machInst, rn,
203                                    RfeOp::DecrementAfter, false);
204                          case 0x1:
205                            return new %(rfe_w)s(machInst, rn,
206                                    RfeOp::DecrementAfter, true);
207                          case 0x4:
208                            return new %(rfe_u)s(machInst, rn,
209                                    RfeOp::IncrementAfter, false);
210                          case 0x5:
211                            return new %(rfe_uw)s(machInst, rn,
212                                    RfeOp::IncrementAfter, true);
213                          case 0x8:
214                            return new %(rfe_p)s(machInst, rn,
215                                    RfeOp::DecrementBefore, false);
216                          case 0x9:
217                            return new %(rfe_pw)s(machInst, rn,
218                                    RfeOp::DecrementBefore, true);
219                          case 0xc:
220                            return new %(rfe_pu)s(machInst, rn,
221                                    RfeOp::IncrementBefore, false);
222                          case 0xd:
223                            return new %(rfe_puw)s(machInst, rn,
224                                    RfeOp::IncrementBefore, true);
225                        }
226                        return new Unknown(machInst);
227                    }
228                }
229                break;
230              case 0x1:
231                {
232                    const uint32_t imm =
233                        (sext<26>(bits(machInst, 23, 0) << 2)) |
234                        (bits(machInst, 24) << 1);
235                    return new BlxImm(machInst, imm);
236                }
237              case 0x2:
238                if (bits(op1, 0) == 1) {
239                    if (rn == INTREG_PC) {
240                        if (bits(op1, 4, 3) != 0x0) {
241                            return new WarnUnimplemented(
242                                    "ldc, ldc2 (literal)", machInst);
243                        }
244                    } else {
245                        if (op1 == 0xC3 || op1 == 0xC7) {
246                            return new WarnUnimplemented(
247                                    "ldc, ldc2 (immediate)", machInst);
248                        }
249                    }
250                    if (op1 == 0xC5) {
251                        return new WarnUnimplemented("mrrc, mrrc2", machInst);
252                    }
253                } else {
254                    if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
255                        return new WarnUnimplemented("stc, stc2", machInst);
256                    } else if (op1 == 0xC4) {
257                        return new WarnUnimplemented("mcrr, mcrrc", machInst);
258                    }
259                }
260                break;
261              case 0x3:
262                {
263                    const bool op = bits(machInst, 4);
264                    if (op) {
265                        if (bits(op1, 0)) {
266                            return new WarnUnimplemented(
267                                    "mrc, mrc2", machInst);
268                        } else {
269                            return new WarnUnimplemented(
270                                    "mcr, mcr2", machInst);
271                        }
272                    } else {
273                        return new WarnUnimplemented("cdp, cdp2", machInst);
274                    }
275                }
276                break;
277            }
278        }
279        return new Unknown(machInst);
280    }
281    ''' % {
282        "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
283        "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
284        "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
285        "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
286        "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
287        "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
288        "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
289        "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
290        "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
291        "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
292        "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
293        "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
294        "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
295        "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
296        "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
297        "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
298        "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
299        "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
300        "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
301        "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
302        "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
303        "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
304        "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
305        "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
306        "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
307        "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
308        "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
309        "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)
310    };
311}};
312