uncond.isa revision 7191:b2b54b8b3e5b 
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39    decode_block = '''
40    {
41        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42        const uint32_t op1 = bits(machInst, 27, 20);
43        if (bits(op1, 7) == 0) {
44            const uint32_t op2 = bits(machInst, 7, 4);
45            if (op1 == 0x10) {
46                if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47                    return new WarnUnimplemented("setend", machInst);
48                } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49                    return new WarnUnimplemented("cps", machInst);
50                }
51            } else if (bits(op1, 6, 5) == 0x1) {
52                return new WarnUnimplemented(
53                        "Advanced SIMD data-processing", machInst);
54            } else if (bits(op1, 6, 4) == 0x4) {
55                if (bits(op1, 0) == 0) {
56                    return new WarnUnimplemented(
57                            "Advanced SIMD element or structure load/store",
58                            machInst);
59                } else if (bits(op1, 2, 0) == 1) {
60                    // Unallocated memory hint
61                    return new WarnUnimplemented("nop", machInst);
62                } else if (bits(op1, 2, 0) == 5) {
63                    return new WarnUnimplemented("pli", machInst);
64                }
65            } else if (bits(op1, 6, 4) == 0x5) {
66                if (bits(op1, 1, 0) == 0x1) {
67                    return new WarnUnimplemented("pld", machInst);
68                } else if (op1 == 0x57) {
69                    switch (op2) {
70                      case 0x1:
71                        return new WarnUnimplemented("clrex", machInst);
72                      case 0x4:
73                        return new WarnUnimplemented("dsb", machInst);
74                      case 0x5:
75                        return new WarnUnimplemented("dmb", machInst);
76                      case 0x6:
77                        return new WarnUnimplemented("isb", machInst);
78                    }
79                }
80            } else if (bits(op2, 0) == 0) {
81                switch (op1 & 0xf7) {
82                  case 0x61:
83                    // Unallocated memory hint
84                    return new WarnUnimplemented("nop", machInst);
85                  case 0x65:
86                    return new WarnUnimplemented("pli", machInst);
87                  case 0x71:
88                    return new WarnUnimplemented("pld", machInst);
89                }
90            }
91        } else {
92            switch (bits(machInst, 26, 25)) {
93              case 0x0:
94                {
95                    const uint32_t val = ((machInst >> 20) & 0x5);
96                    if (val == 0x4) {
97                        return new WarnUnimplemented("srs", machInst);
98                    } else if (val == 0x1) {
99                        return new WarnUnimplemented("rfe", machInst);
100                    }
101                }
102                break;
103              case 0x1:
104                {
105                    const uint32_t imm =
106                        (sext<26>(bits(machInst, 23, 0) << 2)) |
107                        (bits(machInst, 24) << 1);
108                    return new BlxImm(machInst, imm);
109                }
110              case 0x2:
111                if (bits(op1, 0) == 1) {
112                    if (rn == INTREG_PC) {
113                        if (bits(op1, 4, 3) != 0x0) {
114                            return new WarnUnimplemented(
115                                    "ldc, ldc2 (literal)", machInst);
116                        }
117                    } else {
118                        if (op1 == 0xC3 || op1 == 0xC7) {
119                            return new WarnUnimplemented(
120                                    "ldc, ldc2 (immediate)", machInst);
121                        }
122                    }
123                    if (op1 == 0xC5) {
124                        return new WarnUnimplemented("mrrc, mrrc2", machInst);
125                    }
126                } else {
127                    if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
128                        return new WarnUnimplemented("stc, stc2", machInst);
129                    } else if (op1 == 0xC4) {
130                        return new WarnUnimplemented("mcrr, mcrrc", machInst);
131                    }
132                }
133                break;
134              case 0x3:
135                {
136                    const bool op = bits(machInst, 4);
137                    if (op) {
138                        if (bits(op1, 0)) {
139                            return new WarnUnimplemented(
140                                    "mrc, mrc2", machInst);
141                        } else {
142                            return new WarnUnimplemented(
143                                    "mcr, mcr2", machInst);
144                        }
145                    } else {
146                        return new WarnUnimplemented("cdp, cdp2", machInst);
147                    }
148                }
149                break;
150            }
151        }
152        return new Unknown(machInst);
153    }
154    '''
155}};
156