uncond.isa revision 8868
18868SMatt.Horsnell@arm.com// Copyright (c) 2010-2012 ARM Limited
27191Sgblack@eecs.umich.edu// All rights reserved
37191Sgblack@eecs.umich.edu//
47191Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
57191Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
67191Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
77191Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
87191Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
97191Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
107191Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
117191Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
127191Sgblack@eecs.umich.edu//
137191Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
147191Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
157191Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
167191Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
177191Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
187191Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
197191Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
207191Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
217191Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
227191Sgblack@eecs.umich.edu// this software without specific prior written permission.
237191Sgblack@eecs.umich.edu//
247191Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
257191Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
267191Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
277191Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
287191Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
297191Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
307191Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
317191Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
327191Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
337191Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
347191Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
357191Sgblack@eecs.umich.edu//
367191Sgblack@eecs.umich.edu// Authors: Gabe Black
377191Sgblack@eecs.umich.edu
387191Sgblack@eecs.umich.edudef format ArmUnconditional() {{
397191Sgblack@eecs.umich.edu    decode_block = '''
407191Sgblack@eecs.umich.edu    {
417191Sgblack@eecs.umich.edu        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
427191Sgblack@eecs.umich.edu        const uint32_t op1 = bits(machInst, 27, 20);
437191Sgblack@eecs.umich.edu        if (bits(op1, 7) == 0) {
447191Sgblack@eecs.umich.edu            const uint32_t op2 = bits(machInst, 7, 4);
457191Sgblack@eecs.umich.edu            if (op1 == 0x10) {
467191Sgblack@eecs.umich.edu                if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
477308Sgblack@eecs.umich.edu                    return new Setend(machInst, bits(machInst, 9));
487191Sgblack@eecs.umich.edu                } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
497316Sgblack@eecs.umich.edu                    const bool enable = bits(machInst, 19, 18) == 0x2;
507316Sgblack@eecs.umich.edu                    const uint32_t mods = bits(machInst, 4, 0) |
517316Sgblack@eecs.umich.edu                                          (bits(machInst, 8, 6) << 5) |
527316Sgblack@eecs.umich.edu                                          (bits(machInst, 17) << 8) |
537316Sgblack@eecs.umich.edu                                          ((enable ? 1 : 0) << 9);
547316Sgblack@eecs.umich.edu                    return new Cps(machInst, mods);
557191Sgblack@eecs.umich.edu                }
567191Sgblack@eecs.umich.edu            } else if (bits(op1, 6, 5) == 0x1) {
577435Sgblack@eecs.umich.edu                return decodeNeonData(machInst);
587191Sgblack@eecs.umich.edu            } else if (bits(op1, 6, 4) == 0x4) {
597191Sgblack@eecs.umich.edu                if (bits(op1, 0) == 0) {
607435Sgblack@eecs.umich.edu                    return decodeNeonMem(machInst);
617191Sgblack@eecs.umich.edu                } else if (bits(op1, 2, 0) == 1) {
627191Sgblack@eecs.umich.edu                    // Unallocated memory hint
637248Sgblack@eecs.umich.edu                    return new NopInst(machInst);
647191Sgblack@eecs.umich.edu                } else if (bits(op1, 2, 0) == 5) {
657192Sgblack@eecs.umich.edu                    const bool add = bits(machInst, 23);
667192Sgblack@eecs.umich.edu                    const uint32_t imm12 = bits(machInst, 11, 0);
677192Sgblack@eecs.umich.edu                    if (add) {
687192Sgblack@eecs.umich.edu                        return new %(pli_iadd)s(machInst, INTREG_ZERO,
697192Sgblack@eecs.umich.edu                                                rn, add, imm12);
707192Sgblack@eecs.umich.edu                    } else {
717192Sgblack@eecs.umich.edu                        return new %(pli_isub)s(machInst, INTREG_ZERO,
727192Sgblack@eecs.umich.edu                                                rn, add, imm12);
737192Sgblack@eecs.umich.edu                    }
747191Sgblack@eecs.umich.edu                }
757191Sgblack@eecs.umich.edu            } else if (bits(op1, 6, 4) == 0x5) {
767191Sgblack@eecs.umich.edu                if (bits(op1, 1, 0) == 0x1) {
777192Sgblack@eecs.umich.edu                    const bool add = bits(machInst, 23);
787192Sgblack@eecs.umich.edu                    const bool pldw = bits(machInst, 22);
797192Sgblack@eecs.umich.edu                    const uint32_t imm12 = bits(machInst, 11, 0);
807192Sgblack@eecs.umich.edu                    if (pldw) {
817192Sgblack@eecs.umich.edu                        if (add) {
827192Sgblack@eecs.umich.edu                            return new %(pldw_iadd)s(machInst, INTREG_ZERO,
837192Sgblack@eecs.umich.edu                                                     rn, add, imm12);
847192Sgblack@eecs.umich.edu                        } else {
857192Sgblack@eecs.umich.edu                            return new %(pldw_isub)s(machInst, INTREG_ZERO,
867192Sgblack@eecs.umich.edu                                                     rn, add, imm12);
877192Sgblack@eecs.umich.edu                        }
887192Sgblack@eecs.umich.edu                    } else {
897192Sgblack@eecs.umich.edu                        if (add) {
907192Sgblack@eecs.umich.edu                            return new %(pld_iadd)s(machInst, INTREG_ZERO,
917192Sgblack@eecs.umich.edu                                                    rn, add, imm12);
927192Sgblack@eecs.umich.edu                        } else {
937192Sgblack@eecs.umich.edu                            return new %(pld_isub)s(machInst, INTREG_ZERO,
947192Sgblack@eecs.umich.edu                                                    rn, add, imm12);
957192Sgblack@eecs.umich.edu                        }
967192Sgblack@eecs.umich.edu                    }
977191Sgblack@eecs.umich.edu                } else if (op1 == 0x57) {
987191Sgblack@eecs.umich.edu                    switch (op2) {
997191Sgblack@eecs.umich.edu                      case 0x1:
1007603SGene.Wu@arm.com                        return new Clrex(machInst);
1017191Sgblack@eecs.umich.edu                      case 0x4:
1027605SGene.Wu@arm.com                        return new Dsb(machInst);
1037191Sgblack@eecs.umich.edu                      case 0x5:
1047605SGene.Wu@arm.com                        return new Dmb(machInst);
1057191Sgblack@eecs.umich.edu                      case 0x6:
1067605SGene.Wu@arm.com                        return new Isb(machInst);
1077191Sgblack@eecs.umich.edu                    }
1087191Sgblack@eecs.umich.edu                }
1097191Sgblack@eecs.umich.edu            } else if (bits(op2, 0) == 0) {
1107191Sgblack@eecs.umich.edu                switch (op1 & 0xf7) {
1117191Sgblack@eecs.umich.edu                  case 0x61:
1127191Sgblack@eecs.umich.edu                    // Unallocated memory hint
1137248Sgblack@eecs.umich.edu                    return new NopInst(machInst);
1147191Sgblack@eecs.umich.edu                  case 0x65:
1157192Sgblack@eecs.umich.edu                    {
1167192Sgblack@eecs.umich.edu                        const uint32_t imm5 = bits(machInst, 11, 7);
1177192Sgblack@eecs.umich.edu                        const uint32_t type = bits(machInst, 6, 5);
1187192Sgblack@eecs.umich.edu                        const bool add = bits(machInst, 23);
1197192Sgblack@eecs.umich.edu                        const IntRegIndex rm =
1207192Sgblack@eecs.umich.edu                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
1217192Sgblack@eecs.umich.edu                        if (add) {
1227192Sgblack@eecs.umich.edu                            return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
1237192Sgblack@eecs.umich.edu                                                    add, imm5, type, rm);
1247192Sgblack@eecs.umich.edu                        } else {
1257192Sgblack@eecs.umich.edu                            return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
1267192Sgblack@eecs.umich.edu                                                    add, imm5, type, rm);
1277192Sgblack@eecs.umich.edu                        }
1287192Sgblack@eecs.umich.edu                    }
1297191Sgblack@eecs.umich.edu                  case 0x71:
1307192Sgblack@eecs.umich.edu                  case 0x75:
1317192Sgblack@eecs.umich.edu                    {
1327192Sgblack@eecs.umich.edu                        const uint32_t imm5 = bits(machInst, 11, 7);
1337192Sgblack@eecs.umich.edu                        const uint32_t type = bits(machInst, 6, 5);
1347192Sgblack@eecs.umich.edu                        const bool add = bits(machInst, 23);
1357192Sgblack@eecs.umich.edu                        const bool pldw = bits(machInst, 22);
1367192Sgblack@eecs.umich.edu                        const IntRegIndex rm =
1377192Sgblack@eecs.umich.edu                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
1387192Sgblack@eecs.umich.edu                        if (pldw) {
1397192Sgblack@eecs.umich.edu                            if (add) {
1407192Sgblack@eecs.umich.edu                                return new %(pldw_radd)s(machInst, INTREG_ZERO,
1417192Sgblack@eecs.umich.edu                                                         rn, add, imm5,
1427192Sgblack@eecs.umich.edu                                                         type, rm);
1437192Sgblack@eecs.umich.edu                            } else {
1447192Sgblack@eecs.umich.edu                                return new %(pldw_rsub)s(machInst, INTREG_ZERO,
1457192Sgblack@eecs.umich.edu                                                         rn, add, imm5,
1467192Sgblack@eecs.umich.edu                                                         type, rm);
1477192Sgblack@eecs.umich.edu                            }
1487192Sgblack@eecs.umich.edu                        } else {
1497192Sgblack@eecs.umich.edu                            if (add) {
1507192Sgblack@eecs.umich.edu                                return new %(pld_radd)s(machInst, INTREG_ZERO,
1517192Sgblack@eecs.umich.edu                                                        rn, add, imm5,
1527192Sgblack@eecs.umich.edu                                                        type, rm);
1537192Sgblack@eecs.umich.edu                            } else {
1547192Sgblack@eecs.umich.edu                                return new %(pld_rsub)s(machInst, INTREG_ZERO,
1557192Sgblack@eecs.umich.edu                                                        rn, add, imm5,
1567192Sgblack@eecs.umich.edu                                                        type, rm);
1577192Sgblack@eecs.umich.edu                            }
1587192Sgblack@eecs.umich.edu                        }
1597192Sgblack@eecs.umich.edu                    }
1607191Sgblack@eecs.umich.edu                }
1617191Sgblack@eecs.umich.edu            }
1627191Sgblack@eecs.umich.edu        } else {
1637191Sgblack@eecs.umich.edu            switch (bits(machInst, 26, 25)) {
1647191Sgblack@eecs.umich.edu              case 0x0:
1657191Sgblack@eecs.umich.edu                {
1667191Sgblack@eecs.umich.edu                    const uint32_t val = ((machInst >> 20) & 0x5);
1677191Sgblack@eecs.umich.edu                    if (val == 0x4) {
1687314Sgblack@eecs.umich.edu                        const uint32_t mode = bits(machInst, 4, 0);
1697499Sgblack@eecs.umich.edu                        if (badMode((OperatingMode)mode))
1707499Sgblack@eecs.umich.edu                            return new Unknown(machInst);
1717314Sgblack@eecs.umich.edu                        switch (bits(machInst, 24, 21)) {
1727314Sgblack@eecs.umich.edu                          case 0x2:
1737314Sgblack@eecs.umich.edu                            return new %(srs)s(machInst, mode,
1747314Sgblack@eecs.umich.edu                                    SrsOp::DecrementAfter, false);
1757314Sgblack@eecs.umich.edu                          case 0x3:
1767314Sgblack@eecs.umich.edu                            return new %(srs_w)s(machInst, mode,
1777314Sgblack@eecs.umich.edu                                    SrsOp::DecrementAfter, true);
1787314Sgblack@eecs.umich.edu                          case 0x6:
1797314Sgblack@eecs.umich.edu                            return new %(srs_u)s(machInst, mode,
1807314Sgblack@eecs.umich.edu                                    SrsOp::IncrementAfter, false);
1817314Sgblack@eecs.umich.edu                          case 0x7:
1827314Sgblack@eecs.umich.edu                            return new %(srs_uw)s(machInst, mode,
1837314Sgblack@eecs.umich.edu                                    SrsOp::IncrementAfter, true);
1847314Sgblack@eecs.umich.edu                          case 0xa:
1857314Sgblack@eecs.umich.edu                            return new %(srs_p)s(machInst, mode,
1867314Sgblack@eecs.umich.edu                                    SrsOp::DecrementBefore, false);
1877314Sgblack@eecs.umich.edu                          case 0xb:
1887314Sgblack@eecs.umich.edu                            return new %(srs_pw)s(machInst, mode,
1897314Sgblack@eecs.umich.edu                                    SrsOp::DecrementBefore, true);
1907314Sgblack@eecs.umich.edu                          case 0xe:
1917314Sgblack@eecs.umich.edu                            return new %(srs_pu)s(machInst, mode,
1927314Sgblack@eecs.umich.edu                                    SrsOp::IncrementBefore, false);
1937314Sgblack@eecs.umich.edu                          case 0xf:
1947314Sgblack@eecs.umich.edu                            return new %(srs_puw)s(machInst, mode,
1957314Sgblack@eecs.umich.edu                                    SrsOp::IncrementBefore, true);
1967314Sgblack@eecs.umich.edu                        }
1977314Sgblack@eecs.umich.edu                        return new Unknown(machInst);
1987191Sgblack@eecs.umich.edu                    } else if (val == 0x1) {
1997293Sgblack@eecs.umich.edu                        switch (bits(machInst, 24, 21)) {
2007293Sgblack@eecs.umich.edu                          case 0x0:
2017293Sgblack@eecs.umich.edu                            return new %(rfe)s(machInst, rn,
2027293Sgblack@eecs.umich.edu                                    RfeOp::DecrementAfter, false);
2037293Sgblack@eecs.umich.edu                          case 0x1:
2047293Sgblack@eecs.umich.edu                            return new %(rfe_w)s(machInst, rn,
2057293Sgblack@eecs.umich.edu                                    RfeOp::DecrementAfter, true);
2067293Sgblack@eecs.umich.edu                          case 0x4:
2077293Sgblack@eecs.umich.edu                            return new %(rfe_u)s(machInst, rn,
2087293Sgblack@eecs.umich.edu                                    RfeOp::IncrementAfter, false);
2097293Sgblack@eecs.umich.edu                          case 0x5:
2107293Sgblack@eecs.umich.edu                            return new %(rfe_uw)s(machInst, rn,
2117293Sgblack@eecs.umich.edu                                    RfeOp::IncrementAfter, true);
2127293Sgblack@eecs.umich.edu                          case 0x8:
2137293Sgblack@eecs.umich.edu                            return new %(rfe_p)s(machInst, rn,
2147293Sgblack@eecs.umich.edu                                    RfeOp::DecrementBefore, false);
2157293Sgblack@eecs.umich.edu                          case 0x9:
2167293Sgblack@eecs.umich.edu                            return new %(rfe_pw)s(machInst, rn,
2177293Sgblack@eecs.umich.edu                                    RfeOp::DecrementBefore, true);
2187293Sgblack@eecs.umich.edu                          case 0xc:
2197293Sgblack@eecs.umich.edu                            return new %(rfe_pu)s(machInst, rn,
2207293Sgblack@eecs.umich.edu                                    RfeOp::IncrementBefore, false);
2217293Sgblack@eecs.umich.edu                          case 0xd:
2227293Sgblack@eecs.umich.edu                            return new %(rfe_puw)s(machInst, rn,
2237293Sgblack@eecs.umich.edu                                    RfeOp::IncrementBefore, true);
2247293Sgblack@eecs.umich.edu                        }
2257293Sgblack@eecs.umich.edu                        return new Unknown(machInst);
2267191Sgblack@eecs.umich.edu                    }
2277191Sgblack@eecs.umich.edu                }
2287191Sgblack@eecs.umich.edu                break;
2297191Sgblack@eecs.umich.edu              case 0x1:
2307191Sgblack@eecs.umich.edu                {
2317191Sgblack@eecs.umich.edu                    const uint32_t imm =
2327191Sgblack@eecs.umich.edu                        (sext<26>(bits(machInst, 23, 0) << 2)) |
2337191Sgblack@eecs.umich.edu                        (bits(machInst, 24) << 1);
2347602SGene.Wu@arm.com                    return new BlxImm(machInst, imm, COND_UC);
2357191Sgblack@eecs.umich.edu                }
2367191Sgblack@eecs.umich.edu              case 0x2:
2377421Sgblack@eecs.umich.edu                if (bits(op1, 4, 0) != 0) {
2387421Sgblack@eecs.umich.edu                    if (CPNUM == 0xa || CPNUM == 0xb) {
2397421Sgblack@eecs.umich.edu                        return decodeExtensionRegLoadStore(machInst);
2407421Sgblack@eecs.umich.edu                    }
2417421Sgblack@eecs.umich.edu                    if (bits(op1, 0) == 1) {
2427421Sgblack@eecs.umich.edu                        if (rn == INTREG_PC) {
2437421Sgblack@eecs.umich.edu                            if (bits(op1, 4, 3) != 0x0) {
2447421Sgblack@eecs.umich.edu                                return new WarnUnimplemented(
2457421Sgblack@eecs.umich.edu                                        "ldc, ldc2 (literal)", machInst);
2467421Sgblack@eecs.umich.edu                            }
2477421Sgblack@eecs.umich.edu                        } else {
2487421Sgblack@eecs.umich.edu                            if (op1 == 0xC3 || op1 == 0xC7) {
2497421Sgblack@eecs.umich.edu                                return new WarnUnimplemented(
2507421Sgblack@eecs.umich.edu                                        "ldc, ldc2 (immediate)", machInst);
2517421Sgblack@eecs.umich.edu                            }
2527421Sgblack@eecs.umich.edu                        }
2537421Sgblack@eecs.umich.edu                        if (op1 == 0xC5) {
2547191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2557421Sgblack@eecs.umich.edu                                    "mrrc, mrrc2", machInst);
2567191Sgblack@eecs.umich.edu                        }
2577191Sgblack@eecs.umich.edu                    } else {
2587421Sgblack@eecs.umich.edu                        if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
2597191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2607421Sgblack@eecs.umich.edu                                    "stc, stc2", machInst);
2617421Sgblack@eecs.umich.edu                        } else if (op1 == 0xC4) {
2627421Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2637421Sgblack@eecs.umich.edu                                    "mcrr, mcrrc", machInst);
2647191Sgblack@eecs.umich.edu                        }
2657191Sgblack@eecs.umich.edu                    }
2667191Sgblack@eecs.umich.edu                }
2677191Sgblack@eecs.umich.edu                break;
2687191Sgblack@eecs.umich.edu              case 0x3:
2697421Sgblack@eecs.umich.edu                if (bits(op1, 4) == 0) {
2707357Sgblack@eecs.umich.edu                    if (CPNUM == 0xa || CPNUM == 0xb) {
2717357Sgblack@eecs.umich.edu                        return decodeShortFpTransfer(machInst);
2728868SMatt.Horsnell@arm.com                    } else if (CPNUM == 0xe) {
2738868SMatt.Horsnell@arm.com                        return decodeMcrMrc14(machInst);
2747359Sgblack@eecs.umich.edu                    } else if (CPNUM == 0xf) {
2757359Sgblack@eecs.umich.edu                        return decodeMcrMrc15(machInst);
2767357Sgblack@eecs.umich.edu                    }
2777191Sgblack@eecs.umich.edu                    const bool op = bits(machInst, 4);
2787191Sgblack@eecs.umich.edu                    if (op) {
2797191Sgblack@eecs.umich.edu                        if (bits(op1, 0)) {
2807191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2817191Sgblack@eecs.umich.edu                                    "mrc, mrc2", machInst);
2827191Sgblack@eecs.umich.edu                        } else {
2837191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2847191Sgblack@eecs.umich.edu                                    "mcr, mcr2", machInst);
2857191Sgblack@eecs.umich.edu                        }
2867191Sgblack@eecs.umich.edu                    } else {
2877191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("cdp, cdp2", machInst);
2887191Sgblack@eecs.umich.edu                    }
2897191Sgblack@eecs.umich.edu                }
2907191Sgblack@eecs.umich.edu                break;
2917191Sgblack@eecs.umich.edu            }
2927191Sgblack@eecs.umich.edu        }
2937191Sgblack@eecs.umich.edu        return new Unknown(machInst);
2947191Sgblack@eecs.umich.edu    }
2957192Sgblack@eecs.umich.edu    ''' % {
2967192Sgblack@eecs.umich.edu        "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
2977192Sgblack@eecs.umich.edu        "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
2987192Sgblack@eecs.umich.edu        "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
2997192Sgblack@eecs.umich.edu        "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
3007192Sgblack@eecs.umich.edu        "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
3017192Sgblack@eecs.umich.edu        "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
3027192Sgblack@eecs.umich.edu        "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
3037192Sgblack@eecs.umich.edu        "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
3047192Sgblack@eecs.umich.edu        "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
3057192Sgblack@eecs.umich.edu        "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
3067192Sgblack@eecs.umich.edu        "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
3077293Sgblack@eecs.umich.edu        "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
3087293Sgblack@eecs.umich.edu        "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
3097293Sgblack@eecs.umich.edu        "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
3107293Sgblack@eecs.umich.edu        "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
3117293Sgblack@eecs.umich.edu        "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
3127293Sgblack@eecs.umich.edu        "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
3137293Sgblack@eecs.umich.edu        "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
3147293Sgblack@eecs.umich.edu        "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
3157314Sgblack@eecs.umich.edu        "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
3167314Sgblack@eecs.umich.edu        "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
3177314Sgblack@eecs.umich.edu        "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
3187314Sgblack@eecs.umich.edu        "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
3197314Sgblack@eecs.umich.edu        "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
3207314Sgblack@eecs.umich.edu        "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
3217314Sgblack@eecs.umich.edu        "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
3227314Sgblack@eecs.umich.edu        "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
3237314Sgblack@eecs.umich.edu        "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)
3247192Sgblack@eecs.umich.edu    };
3257191Sgblack@eecs.umich.edu}};
326