pred.isa revision 7133:4a1af4580b7d
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43let {{ 44 45 calcCcCode = ''' 46 if (%(canOverflow)s){ 47 cprintf("canOverflow: %%d\\n", Rd < resTemp); 48 replaceBits(CondCodes, 27, Rd < resTemp); 49 } else { 50 uint16_t _ic, _iv, _iz, _in; 51 _in = (resTemp >> %(negBit)d) & 1; 52 _iz = (resTemp == 0); 53 _iv = %(ivValue)s & 1; 54 _ic = %(icValue)s & 1; 55 56 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 57 (CondCodes & 0x0FFFFFFF); 58 59 DPRINTF(Arm, "in = %%d\\n", _in); 60 DPRINTF(Arm, "iz = %%d\\n", _iz); 61 DPRINTF(Arm, "ic = %%d\\n", _ic); 62 DPRINTF(Arm, "iv = %%d\\n", _iv); 63 } 64 ''' 65}}; 66 67let {{ 68 def getCcCode(flagtype): 69 icReg = icImm = iv = '' 70 negBit = 31 71 canOverflow = 'false' 72 73 if flagtype == "none": 74 icReg = icImm = 'CondCodes<29:>' 75 iv = 'CondCodes<28:>' 76 elif flagtype == "llbit": 77 icReg = icImm = 'CondCodes<29:>' 78 iv = 'CondCodes<28:>' 79 negBit = 63 80 elif flagtype == "overflow": 81 canOverflow = "true" 82 icReg = icImm = iv = '0' 83 elif flagtype == "add": 84 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)' 85 iv = 'findOverflow(32, resTemp, Rn, op2)' 86 elif flagtype == "sub": 87 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)' 88 iv = 'findOverflow(32, resTemp, Rn, ~op2)' 89 elif flagtype == "rsb": 90 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)' 91 iv = 'findOverflow(32, resTemp, op2, ~Rn)' 92 else: 93 icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodes<29:>)' 94 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodes<29:>)' 95 iv = 'CondCodes<28:>' 96 return (calcCcCode % {"icValue" : icReg, 97 "ivValue" : iv, 98 "negBit" : negBit, 99 "canOverflow" : canOverflow }, 100 calcCcCode % {"icValue" : icImm, 101 "ivValue" : iv, 102 "negBit" : negBit, 103 "canOverflow" : canOverflow }) 104 105 def getImmCcCode(flagtype): 106 ivValue = icValue = '' 107 negBit = 31 108 canOverflow = 'false' 109 if flagtype == "none": 110 icValue = 'CondCodes<29:>' 111 ivValue = 'CondCodes<28:>' 112 elif flagtype == "llbit": 113 icValue = 'CondCodes<29:>' 114 ivValue = 'CondCodes<28:>' 115 negBit = 63 116 elif flagtype == "overflow": 117 icVaule = ivValue = '0' 118 canOverflow = "true" 119 elif flagtype == "add": 120 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)' 121 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)' 122 elif flagtype == "sub": 123 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)' 124 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)' 125 elif flagtype == "rsb": 126 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)' 127 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)' 128 elif flagtype == "modImm": 129 icValue = 'rotated_carry' 130 ivValue = 'CondCodes<28:>' 131 else: 132 icValue = '(rotate ? rotated_carry:CondCodes<29:>)' 133 ivValue = 'CondCodes<28:>' 134 return calcCcCode % vars() 135}}; 136 137def format DataOp(code, flagtype = logic) {{ 138 (regCcCode, immCcCode) = getCcCode(flagtype) 139 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>, 140 shift, CondCodes<29:>); 141 op2 = op2;''' + code 142 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, 143 shift, CondCodes<29:>); 144 op2 = op2;''' + code 145 regIop = InstObjParams(name, Name, 'PredIntOp', 146 {"code": regCode, 147 "predicate_test": predicateTest}) 148 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp', 149 {"code": immCode, 150 "predicate_test": predicateTest}) 151 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp', 152 {"code": regCode + regCcCode, 153 "predicate_test": predicateTest}) 154 immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp', 155 {"code": immCode + immCcCode, 156 "predicate_test": predicateTest}) 157 header_output = BasicDeclare.subst(regIop) + \ 158 BasicDeclare.subst(immIop) + \ 159 BasicDeclare.subst(regCcIop) + \ 160 BasicDeclare.subst(immCcIop) 161 decoder_output = BasicConstructor.subst(regIop) + \ 162 BasicConstructor.subst(immIop) + \ 163 BasicConstructor.subst(regCcIop) + \ 164 BasicConstructor.subst(immCcIop) 165 exec_output = PredOpExecute.subst(regIop) + \ 166 PredOpExecute.subst(immIop) + \ 167 PredOpExecute.subst(regCcIop) + \ 168 PredOpExecute.subst(immCcIop) 169 decode_block = DataDecode.subst(regIop) 170}}; 171 172def format DataImmOp(code, flagtype = logic) {{ 173 code += "resTemp = resTemp;" 174 iop = InstObjParams(name, Name, 'PredImmOp', 175 {"code": code, 176 "predicate_test": predicateTest}) 177 ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp', 178 {"code": code + getImmCcCode(flagtype), 179 "predicate_test": predicateTest}) 180 header_output = BasicDeclare.subst(iop) + \ 181 BasicDeclare.subst(ccIop) 182 decoder_output = BasicConstructor.subst(iop) + \ 183 BasicConstructor.subst(ccIop) 184 exec_output = PredOpExecute.subst(iop) + \ 185 PredOpExecute.subst(ccIop) 186 decode_block = DataImmDecode.subst(iop) 187}}; 188 189def format DataModImmOp(code, flagtype = modImm) {{ 190 code += "resTemp = resTemp;" 191 iop = InstObjParams(name, Name + "ModImm", 'PredModImmOp', 192 {"code": code, 193 "predicate_test": predicateTest}) 194 ccIop = InstObjParams(name, Name + "ModImmCc", 'PredModImmOp', 195 {"code": code + getImmCcCode(flagtype), 196 "predicate_test": predicateTest}) 197 header_output = BasicDeclare.subst(iop) + \ 198 BasicDeclare.subst(ccIop) 199 decoder_output = BasicConstructor.subst(iop) + \ 200 BasicConstructor.subst(ccIop) 201 exec_output = PredOpExecute.subst(iop) + \ 202 PredOpExecute.subst(ccIop) 203 decode_block = DataImmDecode.subst(iop) 204}}; 205 206def format PredOp(code, *opt_flags) {{ 207 iop = InstObjParams(name, Name, 'PredOp', 208 {"code": code, 209 "predicate_test": predicateTest}, 210 opt_flags) 211 header_output = BasicDeclare.subst(iop) 212 decoder_output = BasicConstructor.subst(iop) 213 decode_block = BasicDecode.subst(iop) 214 exec_output = PredOpExecute.subst(iop) 215}}; 216 217def format PredImmOp(code, *opt_flags) {{ 218 iop = InstObjParams(name, Name, 'PredImmOp', 219 {"code": code, 220 "predicate_test": predicateTest}, 221 opt_flags) 222 header_output = BasicDeclare.subst(iop) 223 decoder_output = BasicConstructor.subst(iop) 224 decode_block = BasicDecode.subst(iop) 225 exec_output = PredOpExecute.subst(iop) 226}}; 227 228def format PredImmOpCc(code, icValue, ivValue, *opt_flags) {{ 229 ccCode = calcCcCode % vars() 230 code += ccCode; 231 iop = InstObjParams(name, Name, 'PredImmOp', 232 {"code": code, 233 "cc_code": ccCode, 234 "predicate_test": predicateTest}, 235 opt_flags) 236 header_output = BasicDeclare.subst(iop) 237 decoder_output = BasicConstructor.subst(iop) 238 decode_block = BasicDecode.subst(iop) 239 exec_output = PredOpExecute.subst(iop) 240}}; 241 242def format PredIntOp(code, *opt_flags) {{ 243 new_code = ArmGenericCodeSubs(code) 244 iop = InstObjParams(name, Name, 'PredIntOp', 245 {"code": new_code, 246 "predicate_test": predicateTest}, 247 opt_flags) 248 header_output = BasicDeclare.subst(iop) 249 decoder_output = BasicConstructor.subst(iop) 250 decode_block = BasicDecode.subst(iop) 251 exec_output = PredOpExecute.subst(iop) 252}}; 253 254def format PredIntOpCc(code, icValue, ivValue, *opt_flags) {{ 255 ccCode = calcCcCode % vars() 256 code += ccCode; 257 new_code = ArmGenericCodeSubs(code) 258 iop = InstObjParams(name, Name, 'PredIntOp', 259 {"code": new_code, 260 "cc_code": ccCode, 261 "predicate_test": predicateTest}, 262 opt_flags) 263 header_output = BasicDeclare.subst(iop) 264 decoder_output = BasicConstructor.subst(iop) 265 decode_block = BasicDecode.subst(iop) 266 exec_output = PredOpExecute.subst(iop) 267}}; 268 269