mem.isa revision 7124:50d26210c812 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Memory-format instructions
46//
47
48def template LoadStoreDeclare {{
49    /**
50     * Static instruction class for "%(mnemonic)s".
51     */
52    class %(class_name)s : public %(base_class)s
53    {
54      public:
55
56        /// Constructor.
57        %(class_name)s(ExtMachInst machInst);
58
59        %(BasicExecDeclare)s
60
61        %(InitiateAccDeclare)s
62
63        %(CompleteAccDeclare)s
64    };
65}};
66
67
68def template InitiateAccDeclare {{
69    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
70}};
71
72
73def template CompleteAccDeclare {{
74    Fault completeAcc(PacketPtr,  %(CPU_exec_context)s *, Trace::InstRecord *) const;
75}};
76
77
78def template LoadStoreConstructor {{
79    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
80         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
81    {
82        %(constructor)s;
83    }
84}};
85
86let {{
87    def buildPUBWLCase(p, u, b, w, l):
88        return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
89
90    def buildMode3Inst(p, u, i, w, type, code, mnem):
91        op = ("-", "+")[u]
92        offset = ("%s Rm", "%s hilo")[i] % op
93        ea_code = "EA = Rn %s;" % ("", offset)[p]
94        if p == 0 or w == 1:
95            code += "Rn = Rn %s;" % offset
96        newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w)
97        suffix = ("Reg", "Hilo")[i]
98        return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
99                ea_code, code, mem_flags = [], inst_flags = [],
100                base_class = 'Memory' + suffix,
101                exec_template_base = type.capitalize())
102}};
103
104def format AddrMode2(imm) {{
105    if eval(imm):
106        imm = True
107    else:
108        imm = False
109
110    header_output = decoder_output = exec_output = ""
111    decode_block = "switch(PUBWL) {\n"
112
113    # Loop over all the values of p, u, b, w and l and build instructions and
114    # a decode block for them.
115    for p in (0, 1):
116        for u in (0, 1):
117            for b in (0, 1):
118                for w in (0, 1):
119                    post = (p == 0)
120                    user = (p == 0 and w == 0)
121                    writeback = (p == 0 or w == 1)
122                    add = (u == 1)
123                    if b == 0:
124                        size = 4
125                    else:
126                        size = 1
127                    if add:
128                        addStr = "true"
129                    else:
130                        addStr = "false"
131                    if imm:
132                        newDecode = "return new %s(machInst, RD, RN," + \
133                                                  "%s, machInst.immed11_0);"
134                        loadClass = loadImmClassName(post, add, writeback,
135                                                     size, False, user)
136                        storeClass = storeImmClassName(post, add, writeback,
137                                                       size, False, user)
138                        loadDecode = newDecode % (loadClass, addStr)
139                        storeDecode = newDecode % (storeClass, addStr)
140                    else:
141                        newDecode = "return new %s(machInst, RD, RN, %s," + \
142                                                  "machInst.shiftSize," + \
143                                                  "machInst.shift, RM);"
144                        loadClass = loadRegClassName(post, add, writeback,
145                                                     size, False, user)
146                        storeClass = storeRegClassName(post, add, writeback,
147                                                       size, False, user)
148                        loadDecode = newDecode % (loadClass, addStr)
149                        storeDecode = newDecode % (storeClass, addStr)
150                    decode = '''
151                        case %#x:
152                          {%s}
153                          break;
154                    '''
155                    decode_block += decode % \
156                        (buildPUBWLCase(p,u,b,w,1), loadDecode)
157                    decode_block += decode % \
158                        (buildPUBWLCase(p,u,b,w,0), storeDecode)
159    decode_block += '''
160        default:
161          return new Unknown(machInst);
162        break;
163    }'''
164}};
165
166def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{
167    l0Code = ArmGenericCodeSubs(l0Code);
168    l1Code = ArmGenericCodeSubs(l1Code);
169
170    header_output = decoder_output = exec_output = ""
171    decode_block = "switch(PUBWL) {\n"
172    (l0Mnem, l1Mnem) = name.split("_");
173
174    # Loop over all the values of p, u, i, w and l and build instructions and
175    # a decode block for them.
176    for (l, type, code, mnem) in ((0, l0Type, l0Code, l0Mnem),
177                                  (1, l1Type, l1Code, l1Mnem)):
178        for p in (0, 1):
179            wset = (0, 1)
180            if (p == 0):
181                wset = (0,)
182            for u in (0, 1):
183                for i in (0, 1):
184                    for w in wset:
185                        (new_header_output,
186                         new_decoder_output,
187                         new_decode_block,
188                         new_exec_output) = buildMode3Inst(p, u, i, w,
189                                                           type, code, mnem)
190                        header_output += new_header_output
191                        decoder_output += new_decoder_output
192                        exec_output += new_exec_output
193                        decode_block += '''
194                            case %#x:
195                              {%s}
196                              break;
197                        ''' % (buildPUBWLCase(p,u,i,w,l), new_decode_block)
198
199    decode_block += '''
200        default:
201          return new Unknown(machInst);
202        break;
203    }'''
204}};
205
206def format Thumb32LoadWord() {{
207    decode = '''
208    {
209        uint32_t op1 = bits(machInst, 24, 23);
210        if (bits(op1, 1) == 0) {
211            uint32_t op2 = bits(machInst, 11, 6);
212            if (HTRN == 0xF) {
213                if (UP) {
214                    return new %(literal_u)s(machInst, RT, INTREG_PC,
215                                             true, IMMED_11_0);
216                } else {
217                    return new %(literal)s(machInst, RT, INTREG_PC,
218                                           false, IMMED_11_0);
219                }
220            } else if (op1 == 0x1) {
221                return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0);
222            } else if (op2 == 0) {
223                return new %(register)s(machInst, RT, RN, UP,
224                                        bits(machInst, 5, 4), LSL, RM);
225            } else if ((op2 & 0x3c) == 0x38) {
226                return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0);
227            } else if ((op2 & 0x3c) == 0x30 || //P
228                       (op2 & 0x24) == 0x24) { //W
229                uint32_t puw = bits(machInst, 10, 8);
230                uint32_t imm = IMMED_7_0;
231                switch (puw) {
232                  case 0:
233                  case 2:
234                    // If we're here, either P or W must have been set.
235                    panic("Neither P or W set, but that "
236                            "shouldn't be possible.\\n");
237                  case 1:
238                    return new %(imm_w)s(machInst, RT, RN, false, imm);
239                  case 3:
240                    return new %(imm_uw)s(machInst, RT, RN, true, imm);
241                  case 4:
242                    return new %(imm_p)s(machInst, RT, RN, false, imm);
243                  case 5:
244                    return new %(imm_pw)s(machInst, RT, RN, false, imm);
245                  case 6:
246                    return new %(imm_pu)s(machInst, RT, RN, true, imm);
247                  case 7:
248                    return new %(imm_puw)s(machInst, RT, RN, true, imm);
249                }
250            }
251        } else {
252            return new Unknown(machInst);
253        }
254    }
255    '''
256    classNames = {
257        "literal_u" : loadImmClassName(False, True, False),
258        "literal" : loadImmClassName(False, False, False),
259        "register" : loadRegClassName(False, True, False),
260        "ldrt" : loadImmClassName(False, True, False, user=True),
261        "imm_w" : loadImmClassName(True, False, True),
262        "imm_uw" : loadImmClassName(True, True, True),
263        "imm_p" : loadImmClassName(False, False, False),
264        "imm_pw" : loadImmClassName(False, False, True),
265        "imm_pu" : loadImmClassName(False, True, False),
266        "imm_puw" : loadImmClassName(False, True, True)
267    }
268    decode_block = decode % classNames
269}};
270
271def format Thumb32StoreSingle() {{
272    def buildPuwDecode(size):
273        puwDecode = '''
274                {
275                    uint32_t puw = bits(machInst, 10, 8);
276                    uint32_t imm = IMMED_7_0;
277                    switch (puw) {
278                      case 0:
279                      case 2:
280                        // If we're here, either P or W must have been set.
281                        panic("Neither P or W set, but that "
282                                "shouldn't be possible.\\n");
283                      case 1:
284                        return new %(imm_w)s(machInst, RT, RN, false, imm);
285                      case 3:
286                        return new %(imm_uw)s(machInst, RT, RN, true, imm);
287                      case 4:
288                        return new %(imm_p)s(machInst, RT, RN, false, imm);
289                      case 5:
290                        return new %(imm_pw)s(machInst, RT, RN, false, imm);
291                      case 6:
292                        return new %(imm_pu)s(machInst, RT, RN, true, imm);
293                      case 7:
294                        return new %(imm_puw)s(machInst, RT, RN, true, imm);
295                    }
296                }
297        '''
298        return puwDecode % {
299            "imm_w" : storeImmClassName(True, False, True, size=size),
300            "imm_uw" : storeImmClassName(True, True, True, size=size),
301            "imm_p" : storeImmClassName(False, False, False, size=size),
302            "imm_pw" : storeImmClassName(False, False, True, size=size),
303            "imm_pu" : storeImmClassName(False, True, False, size=size),
304            "imm_puw" : storeImmClassName(False, True, True, size=size)
305        }
306    decode = '''
307    {
308        uint32_t op1 = bits(machInst, 23, 21);
309        uint32_t op2 = bits(machInst, 11, 6);
310        bool op2Puw = ((op2 & 0x24) == 0x24 ||
311                       (op2 & 0x3c) == 0x30);
312        if (op1 == 4) {
313            return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0);
314        } else if (op1 == 0 && op2Puw) {
315            %(strb_puw)s;
316        } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) {
317            return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0);
318        } else if (op1 == 0 && op2 == 0) {
319            return new %(strb_reg)s(machInst, RT, RN, true,
320                                    bits(machInst, 5, 4), LSL, RM);
321        } else if (op1 == 5) {
322            return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0);
323        } else if (op1 == 1 && op2Puw) {
324            %(strh_puw)s;
325        } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) {
326            return new %(strht)s(machInst, RT, RN, true, IMMED_7_0);
327        } else if (op1 == 1 && op2 == 0) {
328            return new %(strh_reg)s(machInst, RT, RN, true,
329                                    bits(machInst, 5, 4), LSL, RM);
330        } else if (op1 == 6) {
331            return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0);
332        } else if (op1 == 2 && op2Puw) {
333            %(str_puw)s;
334        } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) {
335            return new %(strt)s(machInst, RT, RN, true, IMMED_7_0);
336        } else if (op1 == 2 && op2 == 0) {
337            return new %(str_reg)s(machInst, RT, RN, true,
338                                   bits(machInst, 5, 4), LSL, RM);
339        } else {
340            return new Unknown(machInst);
341        }
342    }
343    '''
344    classNames = {
345        "strb_imm" : storeImmClassName(False, True, False, size=1),
346        "strb_puw" : buildPuwDecode(1),
347        "strbt" : storeImmClassName(False, True, False, user=True, size=1),
348        "strb_reg" : storeRegClassName(False, True, False, size=1),
349        "strh_imm" : storeImmClassName(False, True, False, size=2),
350        "strh_puw" : buildPuwDecode(2),
351        "strht" : storeImmClassName(False, True, False, user=True, size=2),
352        "strh_reg" : storeRegClassName(False, True, False, size=2),
353        "str_imm" : storeImmClassName(False, True, False),
354        "str_puw" : buildPuwDecode(4),
355        "strt" : storeImmClassName(False, True, False, user=True),
356        "str_reg" : storeRegClassName(False, True, False)
357    }
358    decode_block = decode % classNames
359}};
360
361def format Thumb16MemReg() {{
362    decode = '''
363    {
364        const uint32_t opb = bits(machInst, 11, 9);
365        const uint32_t rt = bits(machInst, 2, 0);
366        const uint32_t rn = bits(machInst, 5, 3);
367        const uint32_t rm = bits(machInst, 8, 6);
368        switch (opb) {
369          case 0x0:
370            return new %(str)s(machInst, rt, rn, true, 0, LSL, rm);
371          case 0x1:
372            return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm);
373          case 0x2:
374            return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm);
375          case 0x3:
376            return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm);
377          case 0x4:
378            return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm);
379          case 0x5:
380            return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm);
381          case 0x6:
382            return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm);
383          case 0x7:
384            return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm);
385        }
386    }
387    '''
388    classNames = {
389        "str" : storeRegClassName(False, True, False),
390        "strh" : storeRegClassName(False, True, False, size=2),
391        "strb" : storeRegClassName(False, True, False, size=1),
392        "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1),
393        "ldr" : loadRegClassName(False, True, False),
394        "ldrh" : loadRegClassName(False, True, False, size=2),
395        "ldrb" : loadRegClassName(False, True, False, size=1),
396        "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2),
397    }
398    decode_block = decode % classNames
399}};
400
401def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
402                     mem_flags = [], inst_flags = []) {{
403    ea_code = ArmGenericCodeSubs(ea_code)
404    memacc_code = ArmGenericCodeSubs(memacc_code)
405    (header_output, decoder_output, decode_block, exec_output) = \
406        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
407                      decode_template = BasicDecode,
408                      exec_template_base = 'Load')
409}};
410
411def format ArmStoreMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
412                     mem_flags = [], inst_flags = []) {{
413    ea_code = ArmGenericCodeSubs(ea_code)
414    memacc_code = ArmGenericCodeSubs(memacc_code)
415    (header_output, decoder_output, decode_block, exec_output) = \
416        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
417                      exec_template_base = 'Store')
418}};
419
420