mem.isa revision 7119:5ad962dec52f 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Memory-format instructions
46//
47
48def template LoadStoreDeclare {{
49    /**
50     * Static instruction class for "%(mnemonic)s".
51     */
52    class %(class_name)s : public %(base_class)s
53    {
54      public:
55
56        /// Constructor.
57        %(class_name)s(ExtMachInst machInst);
58
59        %(BasicExecDeclare)s
60
61        %(InitiateAccDeclare)s
62
63        %(CompleteAccDeclare)s
64    };
65}};
66
67
68def template InitiateAccDeclare {{
69    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
70}};
71
72
73def template CompleteAccDeclare {{
74    Fault completeAcc(PacketPtr,  %(CPU_exec_context)s *, Trace::InstRecord *) const;
75}};
76
77
78def template LoadStoreConstructor {{
79    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
80         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
81    {
82        %(constructor)s;
83    }
84}};
85
86
87def template StoreExecute {{
88    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
89                                  Trace::InstRecord *traceData) const
90    {
91        Addr EA;
92        Fault fault = NoFault;
93
94        %(op_decl)s;
95        %(op_rd)s;
96        %(ea_code)s;
97
98        if (%(predicate_test)s)
99        {
100            if (fault == NoFault) {
101                %(memacc_code)s;
102            }
103
104            if (fault == NoFault) {
105                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
106                                  memAccessFlags, NULL);
107            }
108
109            if (fault == NoFault) {
110                %(op_wb)s;
111            }
112        }
113
114        return fault;
115    }
116}};
117
118def template StoreInitiateAcc {{
119    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
120                                      Trace::InstRecord *traceData) const
121    {
122        Addr EA;
123        Fault fault = NoFault;
124
125        %(op_decl)s;
126        %(op_rd)s;
127        %(ea_code)s;
128
129        if (%(predicate_test)s)
130        {
131            if (fault == NoFault) {
132                %(memacc_code)s;
133            }
134
135            if (fault == NoFault) {
136                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
137                                  memAccessFlags, NULL);
138            }
139
140            // Need to write back any potential address register update
141            if (fault == NoFault) {
142                %(op_wb)s;
143            }
144        }
145
146        return fault;
147    }
148}};
149
150
151def template StoreCompleteAcc {{
152    Fault %(class_name)s::completeAcc(PacketPtr pkt,
153                                      %(CPU_exec_context)s *xc,
154                                      Trace::InstRecord *traceData) const
155    {
156        Fault fault = NoFault;
157
158        %(op_decl)s;
159        %(op_rd)s;
160
161        if (%(predicate_test)s)
162        {
163            if (fault == NoFault) {
164                %(op_wb)s;
165            }
166        }
167
168        return fault;
169    }
170}};
171
172def template StoreCondCompleteAcc {{
173    Fault %(class_name)s::completeAcc(PacketPtr pkt,
174                                      %(CPU_exec_context)s *xc,
175                                      Trace::InstRecord *traceData) const
176    {
177        Fault fault = NoFault;
178
179        %(op_dest_decl)s;
180
181        if (%(predicate_test)s)
182        {
183            if (fault == NoFault) {
184                %(op_wb)s;
185            }
186        }
187
188        return fault;
189    }
190}};
191
192let {{
193    def buildPUBWLCase(p, u, b, w, l):
194        return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
195
196    def buildMode2Inst(p, u, b, w, l, suffix, offset):
197        mnem = ("str", "ldr")[l]
198        op = ("-", "+")[u]
199        offset = op + ArmGenericCodeSubs(offset);
200        mem = ("Mem", "Mem.ub")[b]
201        code = ("%s = Rd;", "Rd = %s;")[l] % mem
202        ea_code = "EA = Rn %s;" % ("", offset)[p]
203        if p == 0 or w == 1:
204            code += "Rn = Rn %s;" % offset
205        if p == 0 and w == 0:
206            # Here's where we'll tack on a flag to make this a usermode access.
207            mnem += "t"
208        type = ("Store", "Load")[l]
209        newSuffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w)
210        if b == 1:
211            mnem += "b"
212        return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
213                ea_code, code, mem_flags = [], inst_flags = [],
214                base_class = 'Memory' + suffix,
215                exec_template_base = type.capitalize())
216
217    def buildMode3Inst(p, u, i, w, type, code, mnem):
218        op = ("-", "+")[u]
219        offset = ("%s Rm", "%s hilo")[i] % op
220        ea_code = "EA = Rn %s;" % ("", offset)[p]
221        if p == 0 or w == 1:
222            code += "Rn = Rn %s;" % offset
223        newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w)
224        suffix = ("Reg", "Hilo")[i]
225        return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
226                ea_code, code, mem_flags = [], inst_flags = [],
227                base_class = 'Memory' + suffix,
228                exec_template_base = type.capitalize())
229}};
230
231def format AddrMode2(imm, suffix, offset) {{
232    if eval(imm):
233        imm = True
234    else:
235        imm = False
236
237    header_output = decoder_output = exec_output = ""
238    decode_block = "switch(PUBWL) {\n"
239
240    # Loop over all the values of p, u, b, w and l and build instructions and
241    # a decode block for them.
242    for p in (0, 1):
243        for u in (0, 1):
244            for b in (0, 1):
245                for w in (0, 1):
246                    (new_header_output,
247                     new_decoder_output,
248                     new_decode_block,
249                     new_exec_output) = buildMode2Inst(p, u, b, w, 0,
250                                                       suffix, offset)
251                    header_output += new_header_output
252                    decoder_output += new_decoder_output
253                    exec_output += new_exec_output
254                    decode_block += '''
255                        case %#x:
256                          {%s}
257                          break;
258                    ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)
259
260                    post = (p == 0)
261                    user = (p == 0 and w == 0)
262                    writeback = (p == 0 or w == 1)
263                    add = (u == 1)
264                    if b == 0:
265                        size = 4
266                    else:
267                        size = 1
268                    if add:
269                        addStr = "true"
270                    else:
271                        addStr = "false"
272                    if imm:
273                        newDecode = "return new %s(machInst, RD, RN," + \
274                                                  "%s, machInst.immed11_0);"
275                        className = loadImmClassName(post, add, writeback,
276                                                     size, False, user)
277                        newDecode = newDecode % (className, addStr)
278                    else:
279                        newDecode = "return new %s(machInst, RD, RN, %s," + \
280                                                  "machInst.shiftSize," + \
281                                                  "machInst.shift, RM);"
282                        className = loadRegClassName(post, add, writeback,
283                                                     size, False, user)
284                        newDecode = newDecode % (className, addStr)
285                    decode_block += '''
286                        case %#x:
287                          {%s}
288                          break;
289                    ''' % (buildPUBWLCase(p,u,b,w,1), newDecode)
290    decode_block += '''
291        default:
292          return new Unknown(machInst);
293        break;
294    }'''
295}};
296
297def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{
298    l0Code = ArmGenericCodeSubs(l0Code);
299    l1Code = ArmGenericCodeSubs(l1Code);
300
301    header_output = decoder_output = exec_output = ""
302    decode_block = "switch(PUBWL) {\n"
303    (l0Mnem, l1Mnem) = name.split("_");
304
305    # Loop over all the values of p, u, i, w and l and build instructions and
306    # a decode block for them.
307    for (l, type, code, mnem) in ((0, l0Type, l0Code, l0Mnem),
308                                  (1, l1Type, l1Code, l1Mnem)):
309        for p in (0, 1):
310            wset = (0, 1)
311            if (p == 0):
312                wset = (0,)
313            for u in (0, 1):
314                for i in (0, 1):
315                    for w in wset:
316                        (new_header_output,
317                         new_decoder_output,
318                         new_decode_block,
319                         new_exec_output) = buildMode3Inst(p, u, i, w,
320                                                           type, code, mnem)
321                        header_output += new_header_output
322                        decoder_output += new_decoder_output
323                        exec_output += new_exec_output
324                        decode_block += '''
325                            case %#x:
326                              {%s}
327                              break;
328                        ''' % (buildPUBWLCase(p,u,i,w,l), new_decode_block)
329
330    decode_block += '''
331        default:
332          return new Unknown(machInst);
333        break;
334    }'''
335}};
336
337def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
338                     mem_flags = [], inst_flags = []) {{
339    ea_code = ArmGenericCodeSubs(ea_code)
340    memacc_code = ArmGenericCodeSubs(memacc_code)
341    (header_output, decoder_output, decode_block, exec_output) = \
342        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
343                      decode_template = BasicDecode,
344                      exec_template_base = 'Load')
345}};
346
347def format ArmStoreMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
348                     mem_flags = [], inst_flags = []) {{
349    ea_code = ArmGenericCodeSubs(ea_code)
350    memacc_code = ArmGenericCodeSubs(memacc_code)
351    (header_output, decoder_output, decode_block, exec_output) = \
352        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
353                      exec_template_base = 'Store')
354}};
355
356