xref: /gem5/src/arch/arm/isa/formats/mem.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Memory-format instructions
//

def template LoadStoreDeclare {{
    /**
     * Static instruction class for "%(mnemonic)s".
     */
    class %(class_name)s : public %(base_class)s
    {
      public:

        /// Constructor.
        %(class_name)s(ExtMachInst machInst);

        %(BasicExecDeclare)s

        %(InitiateAccDeclare)s

        %(CompleteAccDeclare)s
    };
}};


def template InitiateAccDeclare {{
    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};


def template CompleteAccDeclare {{
    Fault completeAcc(PacketPtr,  %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};


def template LoadStoreConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
    {
        %(constructor)s;
    }
}};


def template StoreExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                  Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                %(memacc_code)s;
            }

            if (fault == NoFault) {
                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                  memAccessFlags, NULL);
            }

            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

def template StoreInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                %(memacc_code)s;
            }

            if (fault == NoFault) {
                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                  memAccessFlags, NULL);
            }

            // Need to write back any potential address register update
            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};


def template StoreCompleteAcc {{
    Fault %(class_name)s::completeAcc(PacketPtr pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

def template StoreCondCompleteAcc {{
    Fault %(class_name)s::completeAcc(PacketPtr pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(op_dest_decl)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

let {{
    def buildPUBWLCase(p, u, b, w, l):
        return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)

    def buildMode2Inst(p, u, b, w, l, suffix, offset):
        mnem = ("str", "ldr")[l]
        op = ("-", "+")[u]
        offset = op + ArmGenericCodeSubs(offset);
        mem = ("Mem", "Mem.ub")[b]
        code = ("%s = Rd;", "Rd = %s;")[l] % mem
        ea_code = "EA = Rn %s;" % ("", offset)[p]
        if p == 0 or w == 1:
            code += "Rn = Rn %s;" % offset
        if p == 0 and w == 0:
            # Here's where we'll tack on a flag to make this a usermode access.
            mnem += "t"
        type = ("Store", "Load")[l]
        newSuffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w)
        if b == 1:
            mnem += "b"
        return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
                ea_code, code, mem_flags = [], inst_flags = [],
                base_class = 'Memory' + suffix,
                exec_template_base = type.capitalize())

    def buildMode3Inst(p, u, i, w, type, code, mnem):
        op = ("-", "+")[u]
        offset = ("%s Rm", "%s hilo")[i] % op
        ea_code = "EA = Rn %s;" % ("", offset)[p]
        if p == 0 or w == 1:
            code += "Rn = Rn %s;" % offset
        newSuffix = "_P%dU%dI%dW%d" % (p, u, i, w)
        suffix = ("Reg", "Hilo")[i]
        return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
                ea_code, code, mem_flags = [], inst_flags = [],
                base_class = 'Memory' + suffix,
                exec_template_base = type.capitalize())
}};

def format AddrMode2(imm, suffix, offset) {{
    if eval(imm):
        imm = True
    else:
        imm = False

    header_output = decoder_output = exec_output = ""
    decode_block = "switch(PUBWL) {\n"

    # Loop over all the values of p, u, b, w and l and build instructions and
    # a decode block for them.
    for p in (0, 1):
        for u in (0, 1):
            for b in (0, 1):
                for w in (0, 1):
                    (new_header_output,
                     new_decoder_output,
                     new_decode_block,
                     new_exec_output) = buildMode2Inst(p, u, b, w, 0,
                                                       suffix, offset)
                    header_output += new_header_output
                    decoder_output += new_decoder_output
                    exec_output += new_exec_output
                    decode_block += '''
                        case %#x:
                          {%s}
                          break;
                    ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)

                    post = (p == 0)
                    user = (p == 0 and w == 0)
                    writeback = (p == 0 or w == 1)
                    add = (u == 1)
                    if b == 0:
                        size = 4
                    else:
                        size = 1
                    if add:
                        addStr = "true"
                    else:
                        addStr = "false"
                    if imm:
                        newDecode = "return new %s(machInst, RD, RN," + \
                                                  "%s, machInst.immed11_0);"
                        className = loadImmClassName(post, add, writeback,
                                                     size, False, user)
                        newDecode = newDecode % (className, addStr)
                    else:
                        newDecode = "return new %s(machInst, RD, RN, %s," + \
                                                  "machInst.shiftSize," + \
                                                  "machInst.shift, RM);"
                        className = loadRegClassName(post, add, writeback,
                                                     size, False, user)
                        newDecode = newDecode % (className, addStr)
                    decode_block += '''
                        case %#x:
                          {%s}
                          break;
                    ''' % (buildPUBWLCase(p,u,b,w,1), newDecode)
    decode_block += '''
        default:
          return new Unknown(machInst);
        break;
    }'''
}};

def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{
    l0Code = ArmGenericCodeSubs(l0Code);
    l1Code = ArmGenericCodeSubs(l1Code);

    header_output = decoder_output = exec_output = ""
    decode_block = "switch(PUBWL) {\n"
    (l0Mnem, l1Mnem) = name.split("_");

    # Loop over all the values of p, u, i, w and l and build instructions and
    # a decode block for them.
    for (l, type, code, mnem) in ((0, l0Type, l0Code, l0Mnem),
                                  (1, l1Type, l1Code, l1Mnem)):
        for p in (0, 1):
            wset = (0, 1)
            if (p == 0):
                wset = (0,)
            for u in (0, 1):
                for i in (0, 1):
                    for w in wset:
                        (new_header_output,
                         new_decoder_output,
                         new_decode_block,
                         new_exec_output) = buildMode3Inst(p, u, i, w,
                                                           type, code, mnem)
                        header_output += new_header_output
                        decoder_output += new_decoder_output
                        exec_output += new_exec_output
                        decode_block += '''
                            case %#x:
                              {%s}
                              break;
                        ''' % (buildPUBWLCase(p,u,i,w,l), new_decode_block)

    decode_block += '''
        default:
          return new Unknown(machInst);
        break;
    }'''
}};

def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
                     mem_flags = [], inst_flags = []) {{
    ea_code = ArmGenericCodeSubs(ea_code)
    memacc_code = ArmGenericCodeSubs(memacc_code)
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      decode_template = BasicDecode,
                      exec_template_base = 'Load')
}};

def format ArmStoreMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
                     mem_flags = [], inst_flags = []) {{
    ea_code = ArmGenericCodeSubs(ea_code)
    memacc_code = ArmGenericCodeSubs(memacc_code)
    (header_output, decoder_output, decode_block, exec_output) = \
        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                      exec_template_base = 'Store')
}};