fp.isa revision 7337:41379badc620
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Floating Point operate instructions 46// 47 48def template FPAExecute {{ 49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 50 { 51 Fault fault = NoFault; 52 53 %(fp_enable_check)s; 54 55 %(op_decl)s; 56 %(op_rd)s; 57 58 if (%(predicate_test)s) { 59 %(code)s; 60 if (fault == NoFault) { 61 %(op_wb)s; 62 } 63 } 64 65 return fault; 66 } 67}}; 68 69def template FloatDoubleDecode {{ 70 { 71 ArmStaticInst *i = NULL; 72 switch (OPCODE_19 << 1 | OPCODE_7) 73 { 74 case 0: 75 i = (ArmStaticInst *)new %(class_name)sS(machInst); 76 break; 77 case 1: 78 i = (ArmStaticInst *)new %(class_name)sD(machInst); 79 break; 80 case 2: 81 case 3: 82 default: 83 panic("Cannot decode float/double nature of the instruction"); 84 } 85 return i; 86 } 87}}; 88 89// Primary format for float point operate instructions: 90def format FloatOp(code, *flags) {{ 91 orig_code = code 92 93 cblk = code 94 iop = InstObjParams(name, Name, 'PredOp', 95 {"code": cblk, 96 "predicate_test": predicateTest}, 97 flags) 98 header_output = BasicDeclare.subst(iop) 99 decoder_output = BasicConstructor.subst(iop) 100 exec_output = FPAExecute.subst(iop) 101 102 sng_cblk = code 103 sng_iop = InstObjParams(name, Name+'S', 'PredOp', 104 {"code": sng_cblk, 105 "predicate_test": predicateTest}, 106 flags) 107 header_output += BasicDeclare.subst(sng_iop) 108 decoder_output += BasicConstructor.subst(sng_iop) 109 exec_output += FPAExecute.subst(sng_iop) 110 111 dbl_code = re.sub(r'\.sf', '.df', orig_code) 112 113 dbl_cblk = dbl_code 114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 115 {"code": dbl_cblk, 116 "predicate_test": predicateTest}, 117 flags) 118 header_output += BasicDeclare.subst(dbl_iop) 119 decoder_output += BasicConstructor.subst(dbl_iop) 120 exec_output += FPAExecute.subst(dbl_iop) 121 122 decode_block = FloatDoubleDecode.subst(iop) 123}}; 124 125let {{ 126 calcFPCcCode = ''' 127 uint16_t _in, _iz, _ic, _iv; 128 129 _in = %(fReg1)s < %(fReg2)s; 130 _iz = %(fReg1)s == %(fReg2)s; 131 _ic = %(fReg1)s >= %(fReg2)s; 132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 133 134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 135 (CondCodes & 0x0FFFFFFF); 136 ''' 137}}; 138 139def format FloatCmp(fReg1, fReg2, *flags) {{ 140 code = calcFPCcCode % vars() 141 iop = InstObjParams(name, Name, 'PredOp', 142 {"code": code, 143 "predicate_test": predicateTest}, 144 flags) 145 header_output = BasicDeclare.subst(iop) 146 decoder_output = BasicConstructor.subst(iop) 147 decode_block = BasicDecode.subst(iop) 148 exec_output = FPAExecute.subst(iop) 149}}; 150 151def format ExtensionRegLoadStore() {{ 152 decode_block = ''' 153 { 154 const uint32_t opcode = bits(machInst, 24, 20); 155 const uint32_t offset = bits(machInst, 7, 0); 156 const bool single = (bits(machInst, 8) == 0); 157 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 158 RegIndex vd; 159 if (single) { 160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 161 bits(machInst, 22)); 162 } else { 163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 164 (bits(machInst, 22) << 5)); 165 } 166 switch (bits(opcode, 4, 3)) { 167 case 0x0: 168 if (bits(opcode, 4, 1) == 0x2 && 169 !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 170 !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 171 if ((bits(machInst, 7, 4) & 0xd) != 1) { 172 break; 173 } 174 const IntRegIndex rt = 175 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 176 const IntRegIndex rt2 = 177 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 178 const bool op = bits(machInst, 20); 179 uint32_t vm; 180 if (single) { 181 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 182 } else { 183 vm = (bits(machInst, 3, 0) << 1) | 184 (bits(machInst, 5) << 5); 185 } 186 if (op) { 187 return new Vmov2Core2Reg(machInst, rt, rt2, 188 (IntRegIndex)vm); 189 } else { 190 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 191 rt, rt2); 192 } 193 } 194 break; 195 case 0x1: 196 switch (bits(opcode, 1, 0)) { 197 case 0x0: 198 return new VLdmStm(machInst, rn, vd, single, 199 true, false, false, offset); 200 case 0x1: 201 return new VLdmStm(machInst, rn, vd, single, 202 true, false, true, offset); 203 case 0x2: 204 return new VLdmStm(machInst, rn, vd, single, 205 true, true, false, offset); 206 case 0x3: 207 // If rn == sp, then this is called vpop. 208 return new VLdmStm(machInst, rn, vd, single, 209 true, true, true, offset); 210 } 211 case 0x2: 212 if (bits(opcode, 1, 0) == 0x2) { 213 // If rn == sp, then this is called vpush. 214 return new VLdmStm(machInst, rn, vd, single, 215 false, true, false, offset); 216 } else if (bits(opcode, 1, 0) == 0x3) { 217 return new VLdmStm(machInst, rn, vd, single, 218 false, true, true, offset); 219 } 220 // Fall through on purpose 221 case 0x3: 222 if (bits(opcode, 1, 0) == 0x0) { 223 return new WarnUnimplemented("vstr", machInst); 224 } else if (bits(opcode, 1, 0) == 0x1) { 225 const bool up = (bits(machInst, 23) == 1); 226 const uint32_t imm = bits(machInst, 7, 0) << 2; 227 RegIndex vd; 228 if (single) { 229 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 230 (bits(machInst, 22))); 231 if (up) { 232 return new %(vldr_us)s(machInst, vd, rn, up, imm); 233 } else { 234 return new %(vldr_s)s(machInst, vd, rn, up, imm); 235 } 236 } else { 237 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 238 (bits(machInst, 22) << 5)); 239 if (up) { 240 return new %(vldr_ud)s(machInst, vd, vd + 1, 241 rn, up, imm); 242 } else { 243 return new %(vldr_d)s(machInst, vd, vd + 1, 244 rn, up, imm); 245 } 246 } 247 } 248 } 249 return new Unknown(machInst); 250 } 251 ''' % { 252 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 253 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 254 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 255 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False) 256 } 257}}; 258 259def format ShortFpTransfer() {{ 260 decode_block = ''' 261 { 262 const uint32_t l = bits(machInst, 20); 263 const uint32_t c = bits(machInst, 8); 264 const uint32_t a = bits(machInst, 23, 21); 265 const uint32_t b = bits(machInst, 6, 5); 266 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 267 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 268 return new Unknown(machInst); 269 } 270 if (l == 0 && c == 0) { 271 if (a == 0) { 272 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 273 bits(machInst, 7); 274 const IntRegIndex rt = 275 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 276 if (bits(machInst, 20) == 1) { 277 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 278 } else { 279 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 280 } 281 } else if (a == 0x7) { 282 const IntRegIndex rt = 283 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 284 uint32_t specReg = bits(machInst, 19, 16); 285 switch (specReg) { 286 case 0: 287 specReg = MISCREG_FPSID; 288 break; 289 case 1: 290 specReg = MISCREG_FPSCR; 291 break; 292 case 8: 293 specReg = MISCREG_FPEXC; 294 break; 295 default: 296 return new Unknown(machInst); 297 } 298 return new Vmsr(machInst, (IntRegIndex)specReg, rt); 299 } 300 } else if (l == 0 && c == 1) { 301 if (bits(a, 2) == 0) { 302 uint32_t vd = (bits(machInst, 7) << 5) | 303 (bits(machInst, 19, 16) << 1); 304 uint32_t index, size; 305 const IntRegIndex rt = 306 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 307 if (bits(machInst, 22) == 1) { 308 size = 8; 309 index = (bits(machInst, 21) << 2) | 310 bits(machInst, 6, 5); 311 } else if (bits(machInst, 5) == 1) { 312 size = 16; 313 index = (bits(machInst, 21) << 1) | 314 bits(machInst, 6); 315 } else if (bits(machInst, 6) == 0) { 316 size = 32; 317 index = bits(machInst, 21); 318 } else { 319 return new Unknown(machInst); 320 } 321 if (index >= (32 / size)) { 322 index -= (32 / size); 323 vd++; 324 } 325 switch (size) { 326 case 8: 327 return new VmovCoreRegB(machInst, (IntRegIndex)vd, 328 rt, index); 329 case 16: 330 return new VmovCoreRegH(machInst, (IntRegIndex)vd, 331 rt, index); 332 case 32: 333 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 334 } 335 } else if (bits(b, 1) == 0) { 336 // A8-594 337 return new WarnUnimplemented("vdup", machInst); 338 } 339 } else if (l == 1 && c == 0) { 340 if (a == 0) { 341 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 342 bits(machInst, 7); 343 const IntRegIndex rt = 344 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 345 if (bits(machInst, 20) == 1) { 346 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 347 } else { 348 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 349 } 350 } else if (a == 7) { 351 const IntRegIndex rt = 352 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 353 uint32_t specReg = bits(machInst, 19, 16); 354 switch (specReg) { 355 case 0: 356 specReg = MISCREG_FPSID; 357 break; 358 case 1: 359 specReg = MISCREG_FPSCR; 360 break; 361 case 6: 362 specReg = MISCREG_MVFR1; 363 break; 364 case 7: 365 specReg = MISCREG_MVFR0; 366 break; 367 case 8: 368 specReg = MISCREG_FPEXC; 369 break; 370 default: 371 return new Unknown(machInst); 372 } 373 return new Vmrs(machInst, rt, (IntRegIndex)specReg); 374 } 375 } else { 376 uint32_t vd = (bits(machInst, 7) << 5) | 377 (bits(machInst, 19, 16) << 1); 378 uint32_t index, size; 379 const IntRegIndex rt = 380 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 381 const bool u = (bits(machInst, 23) == 1); 382 if (bits(machInst, 22) == 1) { 383 size = 8; 384 index = (bits(machInst, 21) << 2) | 385 bits(machInst, 6, 5); 386 } else if (bits(machInst, 5) == 1) { 387 size = 16; 388 index = (bits(machInst, 21) << 1) | 389 bits(machInst, 6); 390 } else if (bits(machInst, 6) == 0 && !u) { 391 size = 32; 392 index = bits(machInst, 21); 393 } else { 394 return new Unknown(machInst); 395 } 396 if (index >= (32 / size)) { 397 index -= (32 / size); 398 vd++; 399 } 400 switch (size) { 401 case 8: 402 if (u) { 403 return new VmovRegCoreUB(machInst, rt, 404 (IntRegIndex)vd, index); 405 } else { 406 return new VmovRegCoreSB(machInst, rt, 407 (IntRegIndex)vd, index); 408 } 409 case 16: 410 if (u) { 411 return new VmovRegCoreUH(machInst, rt, 412 (IntRegIndex)vd, index); 413 } else { 414 return new VmovRegCoreSH(machInst, rt, 415 (IntRegIndex)vd, index); 416 } 417 case 32: 418 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 419 } 420 } 421 return new Unknown(machInst); 422 } 423 ''' 424}}; 425