data.isa revision 7602:cd1930acae4e
1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Gabe Black 37 38def format ArmMiscMedia() {{ 39 decode_block = ''' 40 { 41 const uint32_t op1 = bits(machInst, 22, 20); 42 const uint32_t op2 = bits(machInst, 7, 5); 43 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 44 const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 45 if (op1 == 0 && op2 == 0) { 46 const IntRegIndex rd = 47 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 48 const IntRegIndex rm = 49 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 50 if (ra == 0xf) { 51 return new Usad8(machInst, rd, rn, rm); 52 } else { 53 return new Usada8(machInst, rd, rn, rm, ra); 54 } 55 } else if (bits(op2, 1, 0) == 0x2) { 56 const uint32_t lsb = bits(machInst, 11, 7); 57 const uint32_t msb = lsb + bits(machInst, 20, 16); 58 if (bits(op1, 2, 1) == 0x3) { 59 return new Ubfx(machInst, ra, rn, lsb, msb); 60 } else if (bits(op1, 2, 1) == 0x1) { 61 return new Sbfx(machInst, ra, rn, lsb, msb); 62 } 63 } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) { 64 const uint32_t lsb = bits(machInst, 11, 7); 65 const uint32_t msb = bits(machInst, 20, 16); 66 if (rn == 0xf) { 67 return new Bfc(machInst, ra, ra, lsb, msb); 68 } else { 69 return new Bfi(machInst, ra, rn, lsb, msb); 70 } 71 } 72 return new Unknown(machInst); 73 } 74 ''' 75}}; 76 77def format ArmDataProcReg() {{ 78 pclr = ''' 79 return new %(className)ssRegPclr(machInst, %(dest)s, 80 %(op1)s, rm, imm5, 81 type); 82 ''' 83 instDecode = ''' 84 case %(opcode)#x: 85 if (immShift) { 86 if (setCc) { 87 if (%(dest)s == INTREG_PC) { 88 %(pclr)s 89 } else { 90 return new %(className)sRegCc(machInst, %(dest)s, 91 %(op1)s, rm, imm5, type); 92 } 93 } else { 94 return new %(className)sReg(machInst, %(dest)s, %(op1)s, 95 rm, imm5, type); 96 } 97 } else { 98 if (setCc) { 99 return new %(className)sRegRegCc(machInst, %(dest)s, 100 %(op1)s, rm, rs, type); 101 } else { 102 return new %(className)sRegReg(machInst, %(dest)s, 103 %(op1)s, rm, rs, type); 104 } 105 } 106 break; 107 ''' 108 109 def instCode(opcode, mnem, useDest = True, useOp1 = True): 110 global pclr 111 if useDest: 112 dest = "rd" 113 else: 114 dest = "INTREG_ZERO" 115 if useOp1: 116 op1 = "rn" 117 else: 118 op1 = "INTREG_ZERO" 119 global instDecode, pclrCode 120 substDict = { "className": mnem.capitalize(), 121 "opcode": opcode, 122 "dest": dest, 123 "op1": op1 } 124 if useDest: 125 substDict["pclr"] = pclr % substDict 126 else: 127 substDict["pclr"] = "" 128 return instDecode % substDict 129 130 decode_block = ''' 131 { 132 const bool immShift = (bits(machInst, 4) == 0); 133 const bool setCc = (bits(machInst, 20) == 1); 134 const uint32_t imm5 = bits(machInst, 11, 7); 135 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 136 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 137 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 138 const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 139 const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 140 switch (OPCODE) { 141 ''' 142 decode_block += instCode(0x0, "and") 143 decode_block += instCode(0x1, "eor") 144 decode_block += instCode(0x2, "sub") 145 decode_block += instCode(0x3, "rsb") 146 decode_block += instCode(0x4, "add") 147 decode_block += instCode(0x5, "adc") 148 decode_block += instCode(0x6, "sbc") 149 decode_block += instCode(0x7, "rsc") 150 decode_block += instCode(0x8, "tst", useDest = False) 151 decode_block += instCode(0x9, "teq", useDest = False) 152 decode_block += instCode(0xa, "cmp", useDest = False) 153 decode_block += instCode(0xb, "cmn", useDest = False) 154 decode_block += instCode(0xc, "orr") 155 decode_block += instCode(0xd, "mov", useOp1 = False) 156 decode_block += instCode(0xe, "bic") 157 decode_block += instCode(0xf, "mvn", useOp1 = False) 158 decode_block += ''' 159 default: 160 return new Unknown(machInst); 161 } 162 } 163 ''' 164}}; 165 166def format ArmPackUnpackSatReverse() {{ 167 decode_block = ''' 168 { 169 const uint32_t op1 = bits(machInst, 22, 20); 170 const uint32_t a = bits(machInst, 19, 16); 171 const uint32_t op2 = bits(machInst, 7, 5); 172 if (bits(op2, 0) == 0) { 173 const IntRegIndex rn = 174 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 175 const IntRegIndex rd = 176 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 177 const uint32_t satImm = bits(machInst, 20, 16); 178 const uint32_t imm = bits(machInst, 11, 7); 179 const ArmShiftType type = 180 (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 181 if (op1 == 0) { 182 if (type) { 183 return new PkhtbReg(machInst, rd, (IntRegIndex)a, 184 rn, imm, type); 185 } else { 186 return new PkhbtReg(machInst, rd, (IntRegIndex)a, 187 rn, imm, type); 188 } 189 } else if (bits(op1, 2, 1) == 1) { 190 return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 191 } else if (bits(op1, 2, 1) == 3) { 192 return new Usat(machInst, rd, satImm, rn, imm, type); 193 } 194 return new Unknown(machInst); 195 } 196 switch (op1) { 197 case 0x0: 198 { 199 const IntRegIndex rn = 200 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 201 const IntRegIndex rd = 202 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 203 const IntRegIndex rm = 204 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 205 if (op2 == 0x3) { 206 const uint32_t rotation = 207 (uint32_t)bits(machInst, 11, 10) << 3; 208 if (a == 0xf) { 209 return new Sxtb16(machInst, rd, rotation, rm); 210 } else { 211 return new Sxtab16(machInst, rd, rn, rm, rotation); 212 } 213 } else if (op2 == 0x5) { 214 return new Sel(machInst, rd, rn, rm); 215 } 216 } 217 break; 218 case 0x2: 219 if (op2 == 0x1) { 220 const IntRegIndex rn = 221 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 222 const IntRegIndex rd = 223 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 224 const uint32_t satImm = bits(machInst, 20, 16); 225 return new Ssat16(machInst, rd, satImm + 1, rn); 226 } else if (op2 == 0x3) { 227 const IntRegIndex rn = 228 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 229 const IntRegIndex rd = 230 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 231 const IntRegIndex rm = 232 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 233 const uint32_t rotation = 234 (uint32_t)bits(machInst, 11, 10) << 3; 235 if (a == 0xf) { 236 return new Sxtb(machInst, rd, rotation, rm); 237 } else { 238 return new Sxtab(machInst, rd, rn, rm, rotation); 239 } 240 } 241 break; 242 case 0x3: 243 if (op2 == 0x1) { 244 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 245 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 246 return new Rev(machInst, rd, rm); 247 } else if (op2 == 0x3) { 248 const IntRegIndex rn = 249 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 250 const IntRegIndex rd = 251 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 252 const IntRegIndex rm = 253 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 254 const uint32_t rotation = 255 (uint32_t)bits(machInst, 11, 10) << 3; 256 if (a == 0xf) { 257 return new Sxth(machInst, rd, rotation, rm); 258 } else { 259 return new Sxtah(machInst, rd, rn, rm, rotation); 260 } 261 } else if (op2 == 0x5) { 262 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 263 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 264 return new Rev16(machInst, rd, rm); 265 } 266 break; 267 case 0x4: 268 if (op2 == 0x3) { 269 const IntRegIndex rn = 270 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 271 const IntRegIndex rd = 272 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 273 const IntRegIndex rm = 274 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 275 const uint32_t rotation = 276 (uint32_t)bits(machInst, 11, 10) << 3; 277 if (a == 0xf) { 278 return new Uxtb16(machInst, rd, rotation, rm); 279 } else { 280 return new Uxtab16(machInst, rd, rn, rm, rotation); 281 } 282 } 283 break; 284 case 0x6: 285 if (op2 == 0x1) { 286 const IntRegIndex rn = 287 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 288 const IntRegIndex rd = 289 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 290 const uint32_t satImm = bits(machInst, 20, 16); 291 return new Usat16(machInst, rd, satImm, rn); 292 } else if (op2 == 0x3) { 293 const IntRegIndex rn = 294 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 295 const IntRegIndex rd = 296 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 297 const IntRegIndex rm = 298 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 299 const uint32_t rotation = 300 (uint32_t)bits(machInst, 11, 10) << 3; 301 if (a == 0xf) { 302 return new Uxtb(machInst, rd, rotation, rm); 303 } else { 304 return new Uxtab(machInst, rd, rn, rm, rotation); 305 } 306 } 307 break; 308 case 0x7: 309 { 310 const IntRegIndex rn = 311 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 312 const IntRegIndex rd = 313 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 314 const IntRegIndex rm = 315 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 316 if (op2 == 0x1) { 317 return new Rbit(machInst, rd, rm); 318 } else if (op2 == 0x3) { 319 const uint32_t rotation = 320 (uint32_t)bits(machInst, 11, 10) << 3; 321 if (a == 0xf) { 322 return new Uxth(machInst, rd, rotation, rm); 323 } else { 324 return new Uxtah(machInst, rd, rn, rm, rotation); 325 } 326 } else if (op2 == 0x5) { 327 return new Revsh(machInst, rd, rm); 328 } 329 } 330 break; 331 } 332 return new Unknown(machInst); 333 } 334 ''' 335}}; 336 337def format ArmParallelAddSubtract() {{ 338 decode_block=''' 339 { 340 const uint32_t op1 = bits(machInst, 21, 20); 341 const uint32_t op2 = bits(machInst, 7, 5); 342 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 343 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 344 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 345 if (bits(machInst, 22) == 0) { 346 switch (op1) { 347 case 0x1: 348 switch (op2) { 349 case 0x0: 350 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 351 case 0x1: 352 return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 353 case 0x2: 354 return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 355 case 0x3: 356 return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 357 case 0x4: 358 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 359 case 0x7: 360 return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 361 } 362 break; 363 case 0x2: 364 switch (op2) { 365 case 0x0: 366 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 367 case 0x1: 368 return new QasxReg(machInst, rd, rn, rm, 0, LSL); 369 case 0x2: 370 return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 371 case 0x3: 372 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 373 case 0x4: 374 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 375 case 0x7: 376 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 377 } 378 break; 379 case 0x3: 380 switch (op2) { 381 case 0x0: 382 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 383 case 0x1: 384 return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 385 case 0x2: 386 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 387 case 0x3: 388 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 389 case 0x4: 390 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 391 case 0x7: 392 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 393 } 394 break; 395 } 396 } else { 397 switch (op1) { 398 case 0x1: 399 switch (op2) { 400 case 0x0: 401 return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 402 case 0x1: 403 return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 404 case 0x2: 405 return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 406 case 0x3: 407 return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 408 case 0x4: 409 return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 410 case 0x7: 411 return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 412 } 413 break; 414 case 0x2: 415 switch (op2) { 416 case 0x0: 417 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 418 case 0x1: 419 return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 420 case 0x2: 421 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 422 case 0x3: 423 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 424 case 0x4: 425 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 426 case 0x7: 427 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 428 } 429 break; 430 case 0x3: 431 switch (op2) { 432 case 0x0: 433 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 434 case 0x1: 435 return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 436 case 0x2: 437 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 438 case 0x3: 439 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 440 case 0x4: 441 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 442 case 0x7: 443 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 444 } 445 break; 446 } 447 } 448 return new Unknown(machInst); 449 } 450 ''' 451}}; 452 453def format ArmDataProcImm() {{ 454 pclr = ''' 455 return new %(className)ssImmPclr(machInst, %(dest)s, 456 %(op1)s, imm, false); 457 ''' 458 adr = ''' 459 return new AdrImm(machInst, %(dest)s, %(add)s, 460 imm, false); 461 ''' 462 instDecode = ''' 463 case %(opcode)#x: 464 if (setCc) { 465 if (%(pclrInst)s && %(dest)s == INTREG_PC) { 466 %(pclr)s 467 } else { 468 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 469 imm, rotC); 470 } 471 } else { 472 if (%(adrInst)s && %(op1)s == INTREG_PC) { 473 %(adr)s 474 } else { 475 return new %(className)sImm(machInst, %(dest)s, %(op1)s, 476 imm, rotC); 477 } 478 } 479 break; 480 ''' 481 482 def instCode(opcode, mnem, useDest = True, useOp1 = True): 483 global instDecode, pclr, adr 484 if useDest: 485 dest = "rd" 486 else: 487 dest = "INTREG_ZERO" 488 if useOp1: 489 op1 = "rn" 490 else: 491 op1 = "INTREG_ZERO" 492 substDict = { "className": mnem.capitalize(), 493 "opcode": opcode, 494 "dest": dest, 495 "op1": op1, 496 "adr": "", 497 "adrInst": "false" } 498 if useDest: 499 substDict["pclrInst"] = "true" 500 substDict["pclr"] = pclr % substDict 501 else: 502 substDict["pclrInst"] = "false" 503 substDict["pclr"] = "" 504 return instDecode % substDict 505 506 def adrCode(opcode, mnem, add="1"): 507 global instDecode, pclr, adr 508 substDict = { "className": mnem.capitalize(), 509 "opcode": opcode, 510 "dest": "rd", 511 "op1": "rn", 512 "add": add, 513 "pclrInst": "true", 514 "adrInst": "true" } 515 substDict["pclr"] = pclr % substDict 516 substDict["adr"] = adr % substDict 517 return instDecode % substDict 518 519 decode_block = ''' 520 { 521 const bool setCc = (bits(machInst, 20) == 1); 522 const uint32_t unrotated = bits(machInst, 7, 0); 523 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 524 const bool rotC = (rotation != 0); 525 const uint32_t imm = rotate_imm(unrotated, rotation); 526 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 527 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 528 switch (OPCODE) { 529 ''' 530 decode_block += instCode(0x0, "and") 531 decode_block += instCode(0x1, "eor") 532 decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 533 decode_block += instCode(0x3, "rsb") 534 decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 535 decode_block += instCode(0x5, "adc") 536 decode_block += instCode(0x6, "sbc") 537 decode_block += instCode(0x7, "rsc") 538 decode_block += instCode(0x8, "tst", useDest = False) 539 decode_block += instCode(0x9, "teq", useDest = False) 540 decode_block += instCode(0xa, "cmp", useDest = False) 541 decode_block += instCode(0xb, "cmn", useDest = False) 542 decode_block += instCode(0xc, "orr") 543 decode_block += instCode(0xd, "mov", useOp1 = False) 544 decode_block += instCode(0xe, "bic") 545 decode_block += instCode(0xf, "mvn", useOp1 = False) 546 decode_block += ''' 547 default: 548 return new Unknown(machInst); 549 } 550 } 551 ''' 552}}; 553 554def format ArmSatAddSub() {{ 555 decode_block = ''' 556 { 557 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 558 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 559 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 560 switch (OPCODE) { 561 case 0x8: 562 return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 563 case 0x9: 564 return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 565 case 0xa: 566 return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 567 case 0xb: 568 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 569 default: 570 return new Unknown(machInst); 571 } 572 } 573 ''' 574}}; 575 576def format Thumb32DataProcReg() {{ 577 decode_block = ''' 578 { 579 const uint32_t op1 = bits(machInst, 23, 20); 580 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 581 const uint32_t op2 = bits(machInst, 7, 4); 582 if (bits(machInst, 15, 12) != 0xf) { 583 return new Unknown(machInst); 584 } 585 if (bits(op1, 3) != 1) { 586 if (op2 == 0) { 587 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 588 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 589 switch (bits(op1, 2, 0)) { 590 case 0x0: 591 return new MovRegReg(machInst, rd, 592 INTREG_ZERO, rn, rm, LSL); 593 case 0x1: 594 return new MovRegRegCc(machInst, rd, 595 INTREG_ZERO, rn, rm, LSL); 596 case 0x2: 597 return new MovRegReg(machInst, rd, 598 INTREG_ZERO, rn, rm, LSR); 599 case 0x3: 600 return new MovRegRegCc(machInst, rd, 601 INTREG_ZERO, rn, rm, LSR); 602 case 0x4: 603 return new MovRegReg(machInst, rd, 604 INTREG_ZERO, rn, rm, ASR); 605 case 0x5: 606 return new MovRegRegCc(machInst, rd, 607 INTREG_ZERO, rn, rm, ASR); 608 case 0x6: 609 return new MovRegReg(machInst, rd, 610 INTREG_ZERO, rn, rm, ROR); 611 case 0x7: 612 return new MovRegRegCc(machInst, rd, 613 INTREG_ZERO, rn, rm, ROR); 614 } 615 } else if (bits(op2, 3) == 0) { 616 return new Unknown(machInst); 617 } else { 618 const IntRegIndex rd = 619 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 620 const IntRegIndex rm = 621 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 622 const uint32_t rotation = 623 (uint32_t)bits(machInst, 5, 4) << 3; 624 switch (bits(op1, 2, 0)) { 625 case 0x0: 626 if (rn == 0xf) { 627 return new Sxth(machInst, rd, rotation, rm); 628 } else { 629 return new Sxtah(machInst, rd, rn, rm, rotation); 630 } 631 case 0x1: 632 if (rn == 0xf) { 633 return new Uxth(machInst, rd, rotation, rm); 634 } else { 635 return new Uxtah(machInst, rd, rn, rm, rotation); 636 } 637 case 0x2: 638 if (rn == 0xf) { 639 return new Sxtb16(machInst, rd, rotation, rm); 640 } else { 641 return new Sxtab16(machInst, rd, rn, rm, rotation); 642 } 643 case 0x3: 644 if (rn == 0xf) { 645 return new Uxtb16(machInst, rd, rotation, rm); 646 } else { 647 return new Uxtab16(machInst, rd, rn, rm, rotation); 648 } 649 case 0x4: 650 if (rn == 0xf) { 651 return new Sxtb(machInst, rd, rotation, rm); 652 } else { 653 return new Sxtab(machInst, rd, rn, rm, rotation); 654 } 655 case 0x5: 656 if (rn == 0xf) { 657 return new Uxtb(machInst, rd, rotation, rm); 658 } else { 659 return new Uxtab(machInst, rd, rn, rm, rotation); 660 } 661 default: 662 return new Unknown(machInst); 663 } 664 } 665 } else { 666 if (bits(op2, 3) == 0) { 667 const IntRegIndex rd = 668 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 669 const IntRegIndex rm = 670 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 671 if (bits(op2, 2) == 0x0) { 672 const uint32_t op1 = bits(machInst, 22, 20); 673 const uint32_t op2 = bits(machInst, 5, 4); 674 switch (op2) { 675 case 0x0: 676 switch (op1) { 677 case 0x1: 678 return new Sadd16RegCc(machInst, rd, 679 rn, rm, 0, LSL); 680 case 0x2: 681 return new SasxRegCc(machInst, rd, 682 rn, rm, 0, LSL); 683 case 0x6: 684 return new SsaxRegCc(machInst, rd, 685 rn, rm, 0, LSL); 686 case 0x5: 687 return new Ssub16RegCc(machInst, rd, 688 rn, rm, 0, LSL); 689 case 0x0: 690 return new Sadd8RegCc(machInst, rd, 691 rn, rm, 0, LSL); 692 case 0x4: 693 return new Ssub8RegCc(machInst, rd, 694 rn, rm, 0, LSL); 695 } 696 break; 697 case 0x1: 698 switch (op1) { 699 case 0x1: 700 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 701 case 0x2: 702 return new QasxReg(machInst, rd, rn, rm, 0, LSL); 703 case 0x6: 704 return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 705 case 0x5: 706 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 707 case 0x0: 708 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 709 case 0x4: 710 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 711 } 712 break; 713 case 0x2: 714 switch (op1) { 715 case 0x1: 716 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 717 case 0x2: 718 return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 719 case 0x6: 720 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 721 case 0x5: 722 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 723 case 0x0: 724 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 725 case 0x4: 726 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 727 } 728 break; 729 } 730 } else { 731 const uint32_t op1 = bits(machInst, 22, 20); 732 const uint32_t op2 = bits(machInst, 5, 4); 733 switch (op2) { 734 case 0x0: 735 switch (op1) { 736 case 0x1: 737 return new Uadd16RegCc(machInst, rd, 738 rn, rm, 0, LSL); 739 case 0x2: 740 return new UasxRegCc(machInst, rd, 741 rn, rm, 0, LSL); 742 case 0x6: 743 return new UsaxRegCc(machInst, rd, 744 rn, rm, 0, LSL); 745 case 0x5: 746 return new Usub16RegCc(machInst, rd, 747 rn, rm, 0, LSL); 748 case 0x0: 749 return new Uadd8RegCc(machInst, rd, 750 rn, rm, 0, LSL); 751 case 0x4: 752 return new Usub8RegCc(machInst, rd, 753 rn, rm, 0, LSL); 754 } 755 break; 756 case 0x1: 757 switch (op1) { 758 case 0x1: 759 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 760 case 0x2: 761 return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 762 case 0x6: 763 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 764 case 0x5: 765 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 766 case 0x0: 767 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 768 case 0x4: 769 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 770 } 771 break; 772 case 0x2: 773 switch (op1) { 774 case 0x1: 775 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 776 case 0x2: 777 return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 778 case 0x6: 779 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 780 case 0x5: 781 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 782 case 0x0: 783 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 784 case 0x4: 785 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 786 } 787 break; 788 } 789 } 790 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 791 const uint32_t op1 = bits(machInst, 21, 20); 792 const uint32_t op2 = bits(machInst, 5, 4); 793 const IntRegIndex rd = 794 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 795 const IntRegIndex rm = 796 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 797 switch (op1) { 798 case 0x0: 799 switch (op2) { 800 case 0x0: 801 return new QaddRegCc(machInst, rd, 802 rm, rn, 0, LSL); 803 case 0x1: 804 return new QdaddRegCc(machInst, rd, 805 rm, rn, 0, LSL); 806 case 0x2: 807 return new QsubRegCc(machInst, rd, 808 rm, rn, 0, LSL); 809 case 0x3: 810 return new QdsubRegCc(machInst, rd, 811 rm, rn, 0, LSL); 812 } 813 break; 814 case 0x1: 815 switch (op2) { 816 case 0x0: 817 return new Rev(machInst, rd, rn); 818 case 0x1: 819 return new Rev16(machInst, rd, rn); 820 case 0x2: 821 return new Rbit(machInst, rd, rm); 822 case 0x3: 823 return new Revsh(machInst, rd, rn); 824 } 825 break; 826 case 0x2: 827 if (op2 == 0) { 828 return new Sel(machInst, rd, rn, rm); 829 } 830 break; 831 case 0x3: 832 if (op2 == 0) { 833 return new Clz(machInst, rd, rm); 834 } 835 } 836 } 837 return new Unknown(machInst); 838 } 839 } 840 ''' 841}}; 842 843def format Thumb16ShiftAddSubMoveCmp() {{ 844 decode_block = ''' 845 { 846 const uint32_t imm5 = bits(machInst, 10, 6); 847 const uint32_t imm3 = bits(machInst, 8, 6); 848 const uint32_t imm8 = bits(machInst, 7, 0); 849 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 850 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 851 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 852 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 853 switch (bits(machInst, 13, 11)) { 854 case 0x0: // lsl 855 if (machInst.itstateMask) { 856 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 857 } else { 858 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 859 } 860 case 0x1: // lsr 861 if (machInst.itstateMask) { 862 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 863 } else { 864 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 865 } 866 case 0x2: // asr 867 if (machInst.itstateMask) { 868 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 869 } else { 870 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 871 } 872 case 0x3: 873 switch (bits(machInst, 10, 9)) { 874 case 0x0: 875 if (machInst.itstateMask) { 876 return new AddReg(machInst, rd, rn, rm, 0, LSL); 877 } else { 878 return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 879 } 880 case 0x1: 881 if (machInst.itstateMask) { 882 return new SubReg(machInst, rd, rn, rm, 0, LSL); 883 } else { 884 return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 885 } 886 case 0x2: 887 if (machInst.itstateMask) { 888 return new AddImm(machInst, rd, rn, imm3, true); 889 } else { 890 return new AddImmCc(machInst, rd, rn, imm3, true); 891 } 892 case 0x3: 893 if (machInst.itstateMask) { 894 return new SubImm(machInst, rd, rn, imm3, true); 895 } else { 896 return new SubImmCc(machInst, rd, rn, imm3, true); 897 } 898 } 899 case 0x4: 900 if (machInst.itstateMask) { 901 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false); 902 } else { 903 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 904 } 905 case 0x5: 906 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 907 case 0x6: 908 if (machInst.itstateMask) { 909 return new AddImm(machInst, rd8, rd8, imm8, true); 910 } else { 911 return new AddImmCc(machInst, rd8, rd8, imm8, true); 912 } 913 case 0x7: 914 if (machInst.itstateMask) { 915 return new SubImm(machInst, rd8, rd8, imm8, true); 916 } else { 917 return new SubImmCc(machInst, rd8, rd8, imm8, true); 918 } 919 } 920 } 921 ''' 922}}; 923 924def format Thumb16DataProcessing() {{ 925 decode_block = ''' 926 { 927 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 928 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 929 switch (bits(machInst, 9, 6)) { 930 case 0x0: 931 if (machInst.itstateMask) { 932 return new AndReg(machInst, rdn, rdn, rm, 0, LSL); 933 } else { 934 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 935 } 936 case 0x1: 937 if (machInst.itstateMask) { 938 return new EorReg(machInst, rdn, rdn, rm, 0, LSL); 939 } else { 940 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 941 } 942 case 0x2: //lsl 943 if (machInst.itstateMask) { 944 return new MovRegReg(machInst, rdn, 945 INTREG_ZERO, rdn, rm, LSL); 946 } else { 947 return new MovRegRegCc(machInst, rdn, 948 INTREG_ZERO, rdn, rm, LSL); 949 } 950 case 0x3: //lsr 951 if (machInst.itstateMask) { 952 return new MovRegReg(machInst, rdn, 953 INTREG_ZERO, rdn, rm, LSR); 954 } else { 955 return new MovRegRegCc(machInst, rdn, 956 INTREG_ZERO, rdn, rm, LSR); 957 } 958 case 0x4: //asr 959 if (machInst.itstateMask) { 960 return new MovRegReg(machInst, rdn, 961 INTREG_ZERO, rdn, rm, ASR); 962 } else { 963 return new MovRegRegCc(machInst, rdn, 964 INTREG_ZERO, rdn, rm, ASR); 965 } 966 case 0x5: 967 if (machInst.itstateMask) { 968 return new AdcReg(machInst, rdn, rdn, rm, 0, LSL); 969 } else { 970 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 971 } 972 case 0x6: 973 if (machInst.itstateMask) { 974 return new SbcReg(machInst, rdn, rdn, rm, 0, LSL); 975 } else { 976 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 977 } 978 case 0x7: // ror 979 if (machInst.itstateMask) { 980 return new MovRegReg(machInst, rdn, 981 INTREG_ZERO, rdn, rm, ROR); 982 } else { 983 return new MovRegRegCc(machInst, rdn, 984 INTREG_ZERO, rdn, rm, ROR); 985 } 986 case 0x8: 987 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 988 case 0x9: 989 if (machInst.itstateMask) { 990 return new RsbImm(machInst, rdn, rm, 0, true); 991 } else { 992 return new RsbImmCc(machInst, rdn, rm, 0, true); 993 } 994 case 0xa: 995 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 996 case 0xb: 997 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 998 case 0xc: 999 if (machInst.itstateMask) { 1000 return new OrrReg(machInst, rdn, rdn, rm, 0, LSL); 1001 } else { 1002 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 1003 } 1004 case 0xd: 1005 if (machInst.itstateMask) { 1006 return new Mul(machInst, rdn, rm, rdn); 1007 } else { 1008 return new MulCc(machInst, rdn, rm, rdn); 1009 } 1010 case 0xe: 1011 if (machInst.itstateMask) { 1012 return new BicReg(machInst, rdn, rdn, rm, 0, LSL); 1013 } else { 1014 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 1015 } 1016 case 0xf: 1017 if (machInst.itstateMask) { 1018 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 1019 } else { 1020 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 1021 } 1022 } 1023 } 1024 ''' 1025}}; 1026 1027def format Thumb16SpecDataAndBx() {{ 1028 decode_block = ''' 1029 { 1030 const IntRegIndex rdn = 1031 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 1032 (bits(machInst, 7) << 3)); 1033 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 1034 switch (bits(machInst, 9, 8)) { 1035 case 0x0: 1036 return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 1037 case 0x1: 1038 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 1039 case 0x2: 1040 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 1041 case 0x3: 1042 if (bits(machInst, 7) == 0) { 1043 ConditionCode condCode; 1044 if(machInst.itstateMask) { 1045 condCode = (ConditionCode)(uint8_t)machInst.itstateCond; 1046 } else { 1047 condCode = COND_UC; 1048 } 1049 return new BxReg(machInst, 1050 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 1051 condCode); 1052 } else { 1053 ConditionCode condCode; 1054 if(machInst.itstateMask) { 1055 condCode = (ConditionCode)(uint8_t)machInst.itstateCond; 1056 } else { 1057 condCode = COND_UC; 1058 } 1059 return new BlxReg(machInst, 1060 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 1061 condCode); 1062 } 1063 } 1064 } 1065 ''' 1066}}; 1067 1068def format Thumb16Adr() {{ 1069 decode_block = ''' 1070 { 1071 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 1072 const uint32_t imm8 = bits(machInst, 7, 0) << 2; 1073 return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 1074 } 1075 ''' 1076}}; 1077 1078def format Thumb16AddSp() {{ 1079 decode_block = ''' 1080 { 1081 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 1082 const uint32_t imm8 = bits(machInst, 7, 0) << 2; 1083 return new AddImm(machInst, rd, INTREG_SP, imm8, true); 1084 } 1085 ''' 1086}}; 1087 1088def format ArmMisc() {{ 1089 decode_block = ''' 1090 { 1091 const uint32_t unrotated = bits(machInst, 7, 0); 1092 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 1093 const uint32_t imm = rotate_imm(unrotated, rotation); 1094 const uint8_t byteMask = bits(machInst, 19, 16); 1095 switch (OPCODE) { 1096 case 0x8: 1097 return new MovImm(machInst, (IntRegIndex)(uint32_t)RD, 1098 (IntRegIndex)INTREG_ZERO, 1099 bits(machInst, 11, 0) | (bits(machInst, 19, 16) << 12), 1100 false); 1101 case 0x9: 1102 if (RN == 0) { 1103 switch (IMM) { 1104 case 0x0: 1105 return new NopInst(machInst); 1106#if FULL_SYSTEM 1107 case 0x1: 1108 return new YieldInst(machInst); 1109 case 0x2: 1110 return new WfeInst(machInst); 1111 case 0x3: 1112 return new WfiInst(machInst); 1113 case 0x4: 1114 return new SevInst(machInst); 1115#endif 1116 default: 1117 return new Unknown(machInst); 1118 } 1119 } else { 1120 return new MsrCpsrImm(machInst, imm, byteMask); 1121 } 1122 case 0xa: 1123 { 1124 const uint32_t timm = (bits(machInst, 19, 16) << 12) | 1125 bits(machInst, 11, 0); 1126 return new MovtImm(machInst, (IntRegIndex)(uint32_t)RD, 1127 (IntRegIndex)(uint32_t)RD, timm, true); 1128 } 1129 case 0xb: 1130 return new MsrSpsrImm(machInst, imm, byteMask); 1131 default: 1132 return new Unknown(machInst); 1133 } 1134 } 1135 ''' 1136}}; 1137 1138def format Thumb16Misc() {{ 1139 decode_block = ''' 1140 { 1141 switch (bits(machInst, 11, 8)) { 1142 case 0x0: 1143 if (bits(machInst, 7)) { 1144 return new SubImm(machInst, INTREG_SP, INTREG_SP, 1145 bits(machInst, 6, 0) << 2, true); 1146 } else { 1147 return new AddImm(machInst, INTREG_SP, INTREG_SP, 1148 bits(machInst, 6, 0) << 2, true); 1149 } 1150 case 0x2: 1151 { 1152 const IntRegIndex rd = 1153 (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 1154 const IntRegIndex rm = 1155 (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 1156 switch (bits(machInst, 7, 6)) { 1157 case 0x0: 1158 return new Sxth(machInst, rd, 0, rm); 1159 case 0x1: 1160 return new Sxtb(machInst, rd, 0, rm); 1161 case 0x2: 1162 return new Uxth(machInst, rd, 0, rm); 1163 case 0x3: 1164 return new Uxtb(machInst, rd, 0, rm); 1165 } 1166 } 1167 case 0x1: 1168 case 0x3: 1169 return new Cbz(machInst, 1170 (bits(machInst, 9) << 6) | 1171 (bits(machInst, 7, 3) << 1), 1172 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1173 case 0x4: 1174 case 0x5: 1175 { 1176 const uint32_t m = bits(machInst, 8); 1177 const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 1178 return new LdmStm(machInst, INTREG_SP, false, false, false, 1179 true, false, regList); 1180 } 1181 case 0x6: 1182 { 1183 const uint32_t opBits = bits(machInst, 7, 5); 1184 if (opBits == 2) { 1185 return new Setend(machInst, bits(machInst, 3)); 1186 } else if (opBits == 3) { 1187 const bool enable = (bits(machInst, 4) == 0); 1188 const uint32_t mods = (bits(machInst, 2, 0) << 5) | 1189 ((enable ? 1 : 0) << 9); 1190 return new Cps(machInst, mods); 1191 } 1192 } 1193 case 0xa: 1194 { 1195 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 1196 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 1197 switch (bits(machInst, 7, 6)) { 1198 case 0x0: 1199 return new Rev(machInst, rd, rm); 1200 case 0x1: 1201 return new Rev16(machInst, rd, rm); 1202 case 0x3: 1203 return new Revsh(machInst, rd, rm); 1204 default: 1205 break; 1206 } 1207 } 1208 break; 1209 case 0x9: 1210 case 0xb: 1211 return new Cbnz(machInst, 1212 (bits(machInst, 9) << 6) | 1213 (bits(machInst, 7, 3) << 1), 1214 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1215 case 0xc: 1216 case 0xd: 1217 { 1218 const uint32_t p = bits(machInst, 8); 1219 const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 1220 return new LdmStm(machInst, INTREG_SP, true, true, false, 1221 true, true, regList); 1222 } 1223 case 0xe: 1224 return new BkptInst(machInst); 1225 case 0xf: 1226 if (bits(machInst, 3, 0) != 0) 1227 return new ItInst(machInst); 1228 switch (bits(machInst, 7, 4)) { 1229 case 0x0: 1230 return new NopInst(machInst); 1231 case 0x1: 1232 return new YieldInst(machInst); 1233 case 0x2: 1234 return new WfeInst(machInst); 1235 case 0x3: 1236 return new WfiInst(machInst); 1237 case 0x4: 1238 return new SevInst(machInst); 1239 default: 1240 return new WarnUnimplemented("unallocated_hint", machInst); 1241 } 1242 default: 1243 break; 1244 } 1245 return new Unknown(machInst); 1246 } 1247 ''' 1248}}; 1249 1250def format Thumb32DataProcModImm() {{ 1251 1252 def decInst(mnem, dest="rd", op1="rn"): 1253 return ''' 1254 if (s) { 1255 return new %(mnem)sImmCc(machInst, %(dest)s, 1256 %(op1)s, imm, rotC); 1257 } else { 1258 return new %(mnem)sImm(machInst, %(dest)s, 1259 %(op1)s, imm, rotC); 1260 } 1261 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 1262 1263 decode_block = ''' 1264 { 1265 const uint32_t op = bits(machInst, 24, 21); 1266 const bool s = (bits(machInst, 20) == 1); 1267 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1268 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1269 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 1270 bits(machInst, 14, 12); 1271 const bool rotC = ctrlImm > 3; 1272 const uint32_t dataImm = bits(machInst, 7, 0); 1273 const uint32_t imm = modified_imm(ctrlImm, dataImm); 1274 switch (op) { 1275 case 0x0: 1276 if (rd == INTREG_PC) { 1277 %(tst)s 1278 } else { 1279 %(and)s 1280 } 1281 case 0x1: 1282 %(bic)s 1283 case 0x2: 1284 if (rn == INTREG_PC) { 1285 %(mov)s 1286 } else { 1287 %(orr)s 1288 } 1289 case 0x3: 1290 if (rn == INTREG_PC) { 1291 %(mvn)s 1292 } else { 1293 %(orn)s 1294 } 1295 case 0x4: 1296 if (rd == INTREG_PC) { 1297 %(teq)s 1298 } else { 1299 %(eor)s 1300 } 1301 case 0x8: 1302 if (rd == INTREG_PC) { 1303 %(cmn)s 1304 } else { 1305 %(add)s 1306 } 1307 case 0xa: 1308 %(adc)s 1309 case 0xb: 1310 %(sbc)s 1311 case 0xd: 1312 if (rd == INTREG_PC) { 1313 %(cmp)s 1314 } else { 1315 %(sub)s 1316 } 1317 case 0xe: 1318 %(rsb)s 1319 default: 1320 return new Unknown(machInst); 1321 } 1322 } 1323 ''' % { 1324 "tst" : decInst("Tst", "INTREG_ZERO"), 1325 "and" : decInst("And"), 1326 "bic" : decInst("Bic"), 1327 "mov" : decInst("Mov", op1="INTREG_ZERO"), 1328 "orr" : decInst("Orr"), 1329 "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 1330 "orn" : decInst("Orn"), 1331 "teq" : decInst("Teq", dest="INTREG_ZERO"), 1332 "eor" : decInst("Eor"), 1333 "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 1334 "add" : decInst("Add"), 1335 "adc" : decInst("Adc"), 1336 "sbc" : decInst("Sbc"), 1337 "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 1338 "sub" : decInst("Sub"), 1339 "rsb" : decInst("Rsb") 1340 } 1341}}; 1342 1343def format Thumb32DataProcPlainBin() {{ 1344 decode_block = ''' 1345 { 1346 const uint32_t op = bits(machInst, 24, 20); 1347 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1348 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1349 switch (op) { 1350 case 0x0: 1351 { 1352 const uint32_t imm = bits(machInst, 7, 0) | 1353 (bits(machInst, 14, 12) << 8) | 1354 (bits(machInst, 26) << 11); 1355 if (rn == 0xf) { 1356 return new AdrImm(machInst, rd, (IntRegIndex)1, 1357 imm, false); 1358 } else { 1359 return new AddImm(machInst, rd, rn, imm, true); 1360 } 1361 } 1362 case 0x4: 1363 { 1364 const uint32_t imm = bits(machInst, 7, 0) | 1365 (bits(machInst, 14, 12) << 8) | 1366 (bits(machInst, 26) << 11) | 1367 (bits(machInst, 19, 16) << 12); 1368 return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 1369 } 1370 case 0xa: 1371 { 1372 const uint32_t imm = bits(machInst, 7, 0) | 1373 (bits(machInst, 14, 12) << 8) | 1374 (bits(machInst, 26) << 11); 1375 if (rn == 0xf) { 1376 return new AdrImm(machInst, rd, (IntRegIndex)0, 1377 imm, false); 1378 } else { 1379 return new SubImm(machInst, rd, rn, imm, true); 1380 } 1381 } 1382 case 0xc: 1383 { 1384 const uint32_t imm = bits(machInst, 7, 0) | 1385 (bits(machInst, 14, 12) << 8) | 1386 (bits(machInst, 26) << 11) | 1387 (bits(machInst, 19, 16) << 12); 1388 return new MovtImm(machInst, rd, rd, imm, true); 1389 } 1390 case 0x12: 1391 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1392 const uint32_t satImm = bits(machInst, 4, 0); 1393 return new Ssat16(machInst, rd, satImm + 1, rn); 1394 } 1395 // Fall through on purpose... 1396 case 0x10: 1397 { 1398 const uint32_t satImm = bits(machInst, 4, 0); 1399 const uint32_t imm = bits(machInst, 7, 6) | 1400 (bits(machInst, 14, 12) << 2); 1401 const ArmShiftType type = 1402 (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 1403 return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1404 } 1405 case 0x14: 1406 { 1407 const uint32_t lsb = bits(machInst, 7, 6) | 1408 (bits(machInst, 14, 12) << 2); 1409 const uint32_t msb = lsb + bits(machInst, 4, 0); 1410 return new Sbfx(machInst, rd, rn, lsb, msb); 1411 } 1412 case 0x16: 1413 { 1414 const uint32_t lsb = bits(machInst, 7, 6) | 1415 (bits(machInst, 14, 12) << 2); 1416 const uint32_t msb = bits(machInst, 4, 0); 1417 if (rn == 0xf) { 1418 return new Bfc(machInst, rd, rd, lsb, msb); 1419 } else { 1420 return new Bfi(machInst, rd, rn, lsb, msb); 1421 } 1422 } 1423 case 0x1a: 1424 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1425 const uint32_t satImm = bits(machInst, 4, 0); 1426 return new Usat16(machInst, rd, satImm, rn); 1427 } 1428 // Fall through on purpose... 1429 case 0x18: 1430 { 1431 const uint32_t satImm = bits(machInst, 4, 0); 1432 const uint32_t imm = bits(machInst, 7, 6) | 1433 (bits(machInst, 14, 12) << 2); 1434 const ArmShiftType type = 1435 (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 1436 return new Usat(machInst, rd, satImm, rn, imm, type); 1437 } 1438 case 0x1c: 1439 { 1440 const uint32_t lsb = bits(machInst, 7, 6) | 1441 (bits(machInst, 14, 12) << 2); 1442 const uint32_t msb = lsb + bits(machInst, 4, 0); 1443 return new Ubfx(machInst, rd, rn, lsb, msb); 1444 } 1445 default: 1446 return new Unknown(machInst); 1447 } 1448 } 1449 ''' 1450}}; 1451 1452def format Thumb32DataProcShiftReg() {{ 1453 1454 def decInst(mnem, dest="rd", op1="rn"): 1455 return ''' 1456 if (s) { 1457 return new %(mnem)sRegCc(machInst, %(dest)s, 1458 %(op1)s, rm, amt, type); 1459 } else { 1460 return new %(mnem)sReg(machInst, %(dest)s, 1461 %(op1)s, rm, amt, type); 1462 } 1463 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 1464 1465 decode_block = ''' 1466 { 1467 const uint32_t op = bits(machInst, 24, 21); 1468 const bool s = (bits(machInst, 20) == 1); 1469 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1470 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1471 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1472 const uint32_t amt = (bits(machInst, 14, 12) << 2) | 1473 bits(machInst, 7, 6); 1474 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 1475 switch (op) { 1476 case 0x0: 1477 if (rd == INTREG_PC) { 1478 %(tst)s 1479 } else { 1480 %(and)s 1481 } 1482 case 0x1: 1483 %(bic)s 1484 case 0x2: 1485 if (rn == INTREG_PC) { 1486 %(mov)s 1487 } else { 1488 %(orr)s 1489 } 1490 case 0x3: 1491 if (rn == INTREG_PC) { 1492 %(mvn)s 1493 } else { 1494 %(orn)s 1495 } 1496 case 0x4: 1497 if (rd == INTREG_PC) { 1498 %(teq)s 1499 } else { 1500 %(eor)s 1501 } 1502 case 0x6: 1503 if (type) { 1504 return new PkhtbReg(machInst, rd, rn, rm, amt, type); 1505 } else { 1506 return new PkhbtReg(machInst, rd, rn, rm, amt, type); 1507 } 1508 case 0x8: 1509 if (rd == INTREG_PC) { 1510 %(cmn)s 1511 } else { 1512 %(add)s 1513 } 1514 case 0xa: 1515 %(adc)s 1516 case 0xb: 1517 %(sbc)s 1518 case 0xd: 1519 if (rd == INTREG_PC) { 1520 %(cmp)s 1521 } else { 1522 %(sub)s 1523 } 1524 case 0xe: 1525 %(rsb)s 1526 default: 1527 return new Unknown(machInst); 1528 } 1529 } 1530 ''' % { 1531 "tst" : decInst("Tst", "INTREG_ZERO"), 1532 "and" : decInst("And"), 1533 "bic" : decInst("Bic"), 1534 "mov" : decInst("Mov", op1="INTREG_ZERO"), 1535 "orr" : decInst("Orr"), 1536 "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 1537 "orn" : decInst("Orn"), 1538 "teq" : decInst("Teq", "INTREG_ZERO"), 1539 "eor" : decInst("Eor"), 1540 "cmn" : decInst("Cmn", "INTREG_ZERO"), 1541 "add" : decInst("Add"), 1542 "adc" : decInst("Adc"), 1543 "sbc" : decInst("Sbc"), 1544 "cmp" : decInst("Cmp", "INTREG_ZERO"), 1545 "sub" : decInst("Sub"), 1546 "rsb" : decInst("Rsb") 1547 } 1548}}; 1549