data.isa revision 7255:61445190b527
15409Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 24519Sgblack@eecs.umich.edu// All rights reserved 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edudef format ArmMiscMedia() {{ 394519Sgblack@eecs.umich.edu decode_block = ''' 404519Sgblack@eecs.umich.edu { 414519Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 424519Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 434519Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 444519Sgblack@eecs.umich.edu const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 454519Sgblack@eecs.umich.edu if (op1 == 0 && op2 == 0) { 464519Sgblack@eecs.umich.edu const IntRegIndex rd = 474519Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 484519Sgblack@eecs.umich.edu const IntRegIndex rm = 494519Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 504809Sgblack@eecs.umich.edu if (ra == 0xf) { 514519Sgblack@eecs.umich.edu return new Usad8(machInst, rd, rn, rm); 524519Sgblack@eecs.umich.edu } else { 534688Sgblack@eecs.umich.edu return new Usada8(machInst, rd, rn, rm, ra); 544688Sgblack@eecs.umich.edu } 554688Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x2) { 564688Sgblack@eecs.umich.edu if (bits(op1, 2, 1) == 0x3) { 574688Sgblack@eecs.umich.edu return new WarnUnimplemented("ubfx", machInst); 584688Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 0x1) { 594708Sgblack@eecs.umich.edu return new WarnUnimplemented("sbfx", machInst); 604708Sgblack@eecs.umich.edu } 614708Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) { 624708Sgblack@eecs.umich.edu if (rn == 0xf) { 634519Sgblack@eecs.umich.edu return new WarnUnimplemented("bfc", machInst); 644519Sgblack@eecs.umich.edu } else { 654519Sgblack@eecs.umich.edu return new WarnUnimplemented("bfi", machInst); 664519Sgblack@eecs.umich.edu } 674519Sgblack@eecs.umich.edu } 684519Sgblack@eecs.umich.edu return new Unknown(machInst); 694519Sgblack@eecs.umich.edu } 704519Sgblack@eecs.umich.edu ''' 714519Sgblack@eecs.umich.edu}}; 724519Sgblack@eecs.umich.edu 734519Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 744951Sgblack@eecs.umich.edu pclr = ''' 754519Sgblack@eecs.umich.edu return new %(className)ssRegPclr(machInst, %(dest)s, 764519Sgblack@eecs.umich.edu %(op1)s, rm, imm5, 774519Sgblack@eecs.umich.edu type); 784519Sgblack@eecs.umich.edu ''' 794519Sgblack@eecs.umich.edu instDecode = ''' 804519Sgblack@eecs.umich.edu case %(opcode)#x: 814688Sgblack@eecs.umich.edu if (immShift) { 824688Sgblack@eecs.umich.edu if (setCc) { 834688Sgblack@eecs.umich.edu if (%(dest)s == INTREG_PC) { 844688Sgblack@eecs.umich.edu %(pclr)s 854688Sgblack@eecs.umich.edu } else { 864688Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 874708Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 884708Sgblack@eecs.umich.edu } 894708Sgblack@eecs.umich.edu } else { 904708Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 914519Sgblack@eecs.umich.edu rm, imm5, type); 924519Sgblack@eecs.umich.edu } 934519Sgblack@eecs.umich.edu } else { 944519Sgblack@eecs.umich.edu if (setCc) { 954519Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 964519Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 974519Sgblack@eecs.umich.edu } else { 984519Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 994519Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1004519Sgblack@eecs.umich.edu } 1014519Sgblack@eecs.umich.edu } 1024519Sgblack@eecs.umich.edu break; 1034519Sgblack@eecs.umich.edu ''' 1044519Sgblack@eecs.umich.edu 1054519Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 1067620Sgblack@eecs.umich.edu global pclr 1076345Sgblack@eecs.umich.edu if useDest: 1084712Sgblack@eecs.umich.edu dest = "rd" 1094519Sgblack@eecs.umich.edu else: 1104519Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 1114519Sgblack@eecs.umich.edu if useOp1: 1124519Sgblack@eecs.umich.edu op1 = "rn" 1134519Sgblack@eecs.umich.edu else: 1144519Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 1154519Sgblack@eecs.umich.edu global instDecode, pclrCode 1164951Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 1174519Sgblack@eecs.umich.edu "opcode": opcode, 1184519Sgblack@eecs.umich.edu "dest": dest, 1194951Sgblack@eecs.umich.edu "op1": op1 } 1207620Sgblack@eecs.umich.edu if useDest: 1216646Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 1224712Sgblack@eecs.umich.edu else: 1234519Sgblack@eecs.umich.edu substDict["pclr"] = "" 1244519Sgblack@eecs.umich.edu return instDecode % substDict 1254519Sgblack@eecs.umich.edu 1264519Sgblack@eecs.umich.edu decode_block = ''' 1274519Sgblack@eecs.umich.edu { 1284519Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 1294519Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 1307620Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 1316345Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1324712Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 1337620Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 1344688Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1354581Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1364519Sgblack@eecs.umich.edu switch (OPCODE) { 1377626Sgblack@eecs.umich.edu ''' 1384519Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1394519Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1404519Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1414519Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1424951Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1437620Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1446646Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1454712Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1467620Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1474688Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1484581Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1494519Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1507626Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1514519Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1524519Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1534519Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1545075Sgblack@eecs.umich.edu decode_block += ''' 1555075Sgblack@eecs.umich.edu default: 1565075Sgblack@eecs.umich.edu return new Unknown(machInst); 1575075Sgblack@eecs.umich.edu } 1585428Sgblack@eecs.umich.edu } 1595428Sgblack@eecs.umich.edu ''' 1605674Sgblack@eecs.umich.edu}}; 1615899Sgblack@eecs.umich.edu 1625936Sgblack@eecs.umich.edudef format ArmPackUnpackSatReverse() {{ 1635428Sgblack@eecs.umich.edu decode_block = ''' 1645678Sgblack@eecs.umich.edu { 1655678Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 1665678Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 19, 16); 1675678Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 1685678Sgblack@eecs.umich.edu if (bits(op2, 0) == 0) { 1695678Sgblack@eecs.umich.edu const IntRegIndex rn = 1705678Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1715678Sgblack@eecs.umich.edu const IntRegIndex rd = 1725678Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1735075Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 1745075Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 11, 7); 1755075Sgblack@eecs.umich.edu const ArmShiftType type = 1765075Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1775075Sgblack@eecs.umich.edu if (op1 == 0) { 1785075Sgblack@eecs.umich.edu if (type) { 1795075Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, (IntRegIndex)a, 1805075Sgblack@eecs.umich.edu rn, imm, type); 1817719Sgblack@eecs.umich.edu } else { 1825075Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, (IntRegIndex)a, 1835075Sgblack@eecs.umich.edu rn, imm, type); 1845075Sgblack@eecs.umich.edu } 1855075Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 1) { 1865075Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1875075Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 3) { 1885075Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 1895075Sgblack@eecs.umich.edu } 1905075Sgblack@eecs.umich.edu return new Unknown(machInst); 1915075Sgblack@eecs.umich.edu } 1925075Sgblack@eecs.umich.edu switch (op1) { 1935075Sgblack@eecs.umich.edu case 0x0: 1945075Sgblack@eecs.umich.edu { 1955075Sgblack@eecs.umich.edu const IntRegIndex rn = 1965075Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1975075Sgblack@eecs.umich.edu const IntRegIndex rd = 1985075Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1995075Sgblack@eecs.umich.edu const IntRegIndex rm = 2005075Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2015075Sgblack@eecs.umich.edu if (op2 == 0x3) { 2025075Sgblack@eecs.umich.edu const uint32_t rotation = 2035075Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2045075Sgblack@eecs.umich.edu if (a == 0xf) { 2055075Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 2065075Sgblack@eecs.umich.edu } else { 2074519Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 2085040Sgblack@eecs.umich.edu } 2095040Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2105040Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 2115040Sgblack@eecs.umich.edu } 2125040Sgblack@eecs.umich.edu } 2135040Sgblack@eecs.umich.edu break; 2145040Sgblack@eecs.umich.edu case 0x2: 2155040Sgblack@eecs.umich.edu if (op2 == 0x1) { 2165040Sgblack@eecs.umich.edu const IntRegIndex rn = 2175040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2185040Sgblack@eecs.umich.edu const IntRegIndex rd = 2195040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2205040Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2215040Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 2225040Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2235040Sgblack@eecs.umich.edu const IntRegIndex rn = 2245040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2255040Sgblack@eecs.umich.edu const IntRegIndex rd = 2265040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2275040Sgblack@eecs.umich.edu const IntRegIndex rm = 2285040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2295040Sgblack@eecs.umich.edu const uint32_t rotation = 2305040Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2315040Sgblack@eecs.umich.edu if (a == 0xf) { 2325040Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 2335040Sgblack@eecs.umich.edu } else { 2345040Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 2355040Sgblack@eecs.umich.edu } 2365040Sgblack@eecs.umich.edu } 2375040Sgblack@eecs.umich.edu break; 2385062Sgblack@eecs.umich.edu case 0x3: 2395062Sgblack@eecs.umich.edu if (op2 == 0x1) { 2405062Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2415062Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2425062Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 2435062Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2445062Sgblack@eecs.umich.edu const IntRegIndex rn = 2455040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2465062Sgblack@eecs.umich.edu const IntRegIndex rd = 2475062Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2485062Sgblack@eecs.umich.edu const IntRegIndex rm = 2495062Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2506647Sgblack@eecs.umich.edu const uint32_t rotation = 2515040Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2526647Sgblack@eecs.umich.edu if (a == 0xf) { 2536647Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 2546647Sgblack@eecs.umich.edu } else { 2556647Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 2565040Sgblack@eecs.umich.edu } 2575040Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2585040Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2595040Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2605239Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 2615040Sgblack@eecs.umich.edu } 2625040Sgblack@eecs.umich.edu break; 2635040Sgblack@eecs.umich.edu case 0x4: 2645040Sgblack@eecs.umich.edu if (op2 == 0x3) { 2655040Sgblack@eecs.umich.edu const IntRegIndex rn = 2665040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2675040Sgblack@eecs.umich.edu const IntRegIndex rd = 2685040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2695061Sgblack@eecs.umich.edu const IntRegIndex rm = 2705040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2715040Sgblack@eecs.umich.edu const uint32_t rotation = 2725061Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2735061Sgblack@eecs.umich.edu if (a == 0xf) { 2745061Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 2755061Sgblack@eecs.umich.edu } else { 2765061Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 2775061Sgblack@eecs.umich.edu } 2785061Sgblack@eecs.umich.edu } 2795061Sgblack@eecs.umich.edu break; 2806647Sgblack@eecs.umich.edu case 0x6: 2816647Sgblack@eecs.umich.edu if (op2 == 0x1) { 2826647Sgblack@eecs.umich.edu const IntRegIndex rn = 2835040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2845040Sgblack@eecs.umich.edu const IntRegIndex rd = 2855040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2865040Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2875040Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 2885040Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2896647Sgblack@eecs.umich.edu const IntRegIndex rn = 2905040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2915040Sgblack@eecs.umich.edu const IntRegIndex rd = 2925040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2935040Sgblack@eecs.umich.edu const IntRegIndex rm = 2945040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2955040Sgblack@eecs.umich.edu const uint32_t rotation = 2965040Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2975040Sgblack@eecs.umich.edu if (a == 0xf) { 2985040Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 2995040Sgblack@eecs.umich.edu } else { 3005040Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 3015040Sgblack@eecs.umich.edu } 3025040Sgblack@eecs.umich.edu } 3035040Sgblack@eecs.umich.edu break; 3045040Sgblack@eecs.umich.edu case 0x7: 3055040Sgblack@eecs.umich.edu { 3065040Sgblack@eecs.umich.edu const IntRegIndex rn = 3075040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3084688Sgblack@eecs.umich.edu const IntRegIndex rd = 3095040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3104688Sgblack@eecs.umich.edu const IntRegIndex rm = 3114688Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3124688Sgblack@eecs.umich.edu if (op2 == 0x1) { 3134688Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 3145040Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 3154688Sgblack@eecs.umich.edu const uint32_t rotation = 3165040Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3175040Sgblack@eecs.umich.edu if (a == 0xf) { 3185040Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 3195040Sgblack@eecs.umich.edu } else { 3205040Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 3215040Sgblack@eecs.umich.edu } 3225040Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 3235040Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 3245040Sgblack@eecs.umich.edu } 3255040Sgblack@eecs.umich.edu } 3265040Sgblack@eecs.umich.edu break; 3275040Sgblack@eecs.umich.edu } 3285040Sgblack@eecs.umich.edu return new Unknown(machInst); 3295040Sgblack@eecs.umich.edu } 3305040Sgblack@eecs.umich.edu ''' 3315040Sgblack@eecs.umich.edu}}; 3325040Sgblack@eecs.umich.edu 3335040Sgblack@eecs.umich.edudef format ArmParallelAddSubtract() {{ 3345040Sgblack@eecs.umich.edu decode_block=''' 3355040Sgblack@eecs.umich.edu { 3365040Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 3375040Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 3384688Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3394688Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3405040Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3415040Sgblack@eecs.umich.edu if (bits(machInst, 22) == 0) { 3425040Sgblack@eecs.umich.edu switch (op1) { 3435040Sgblack@eecs.umich.edu case 0x1: 3444688Sgblack@eecs.umich.edu switch (op2) { 3454688Sgblack@eecs.umich.edu case 0x0: 3465040Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3475040Sgblack@eecs.umich.edu case 0x1: 3485040Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 3495040Sgblack@eecs.umich.edu case 0x2: 3505040Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 3515040Sgblack@eecs.umich.edu case 0x3: 3524519Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 3534519Sgblack@eecs.umich.edu case 0x4: 3545040Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 3554688Sgblack@eecs.umich.edu case 0x7: 3564701Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 3574688Sgblack@eecs.umich.edu } 3584688Sgblack@eecs.umich.edu break; 3594688Sgblack@eecs.umich.edu case 0x2: 3604688Sgblack@eecs.umich.edu switch (op2) { 3614688Sgblack@eecs.umich.edu case 0x0: 3624688Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 3634688Sgblack@eecs.umich.edu case 0x1: 3644519Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 3657620Sgblack@eecs.umich.edu case 0x2: 3665040Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 3675040Sgblack@eecs.umich.edu case 0x3: 3685040Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 3697620Sgblack@eecs.umich.edu case 0x4: 3705040Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 3714688Sgblack@eecs.umich.edu case 0x7: 3725040Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 3734519Sgblack@eecs.umich.edu } 3745040Sgblack@eecs.umich.edu break; 3754519Sgblack@eecs.umich.edu case 0x3: 3764519Sgblack@eecs.umich.edu switch (op2) { 3774519Sgblack@eecs.umich.edu case 0x0: 3784539Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 3794519Sgblack@eecs.umich.edu case 0x1: 3805040Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 3814688Sgblack@eecs.umich.edu case 0x2: 3825040Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 3835040Sgblack@eecs.umich.edu case 0x3: 3845115Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 3855040Sgblack@eecs.umich.edu case 0x4: 3865040Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 3875040Sgblack@eecs.umich.edu case 0x7: 3885115Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 3895040Sgblack@eecs.umich.edu } 3905040Sgblack@eecs.umich.edu break; 3914519Sgblack@eecs.umich.edu } 3925040Sgblack@eecs.umich.edu } else { 3935040Sgblack@eecs.umich.edu switch (op1) { 3945040Sgblack@eecs.umich.edu case 0x1: 3955040Sgblack@eecs.umich.edu switch (op2) { 3964519Sgblack@eecs.umich.edu case 0x0: 3975040Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3985040Sgblack@eecs.umich.edu case 0x1: 3995040Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 4005040Sgblack@eecs.umich.edu case 0x2: 4014519Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 4025040Sgblack@eecs.umich.edu case 0x3: 4035040Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 4045083Sgblack@eecs.umich.edu case 0x4: 4054519Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 4065063Sgblack@eecs.umich.edu case 0x7: 4075063Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 4085063Sgblack@eecs.umich.edu } 4095063Sgblack@eecs.umich.edu break; 4105063Sgblack@eecs.umich.edu case 0x2: 4116345Sgblack@eecs.umich.edu switch (op2) { 4126345Sgblack@eecs.umich.edu case 0x0: 4135063Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 4145063Sgblack@eecs.umich.edu case 0x1: 4155063Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 4165063Sgblack@eecs.umich.edu case 0x2: 4176345Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 4186345Sgblack@eecs.umich.edu case 0x3: 4195063Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 4205040Sgblack@eecs.umich.edu case 0x4: 4215040Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 4224595Sgblack@eecs.umich.edu case 0x7: 4235040Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 4245040Sgblack@eecs.umich.edu } 4254595Sgblack@eecs.umich.edu break; 4265040Sgblack@eecs.umich.edu case 0x3: 4275040Sgblack@eecs.umich.edu switch (op2) { 4284732Sgblack@eecs.umich.edu case 0x0: 4295138Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 4305040Sgblack@eecs.umich.edu case 0x1: 4315040Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 4325040Sgblack@eecs.umich.edu case 0x2: 4335040Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 4344732Sgblack@eecs.umich.edu case 0x3: 4355138Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 4365040Sgblack@eecs.umich.edu case 0x4: 4375040Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 4385040Sgblack@eecs.umich.edu case 0x7: 4395040Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 4405040Sgblack@eecs.umich.edu } 4415040Sgblack@eecs.umich.edu break; 4425040Sgblack@eecs.umich.edu } 4435040Sgblack@eecs.umich.edu } 4445040Sgblack@eecs.umich.edu return new Unknown(machInst); 4455040Sgblack@eecs.umich.edu } 4465040Sgblack@eecs.umich.edu ''' 4475063Sgblack@eecs.umich.edu}}; 4485040Sgblack@eecs.umich.edu 4495063Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 4505063Sgblack@eecs.umich.edu pclr = ''' 4516742Svince@csl.cornell.edu return new %(className)ssImmPclr(machInst, %(dest)s, 4526430Sgblack@eecs.umich.edu %(op1)s, imm, false); 4536430Sgblack@eecs.umich.edu ''' 4546430Sgblack@eecs.umich.edu adr = ''' 4556461Sgblack@eecs.umich.edu return new AdrImm(machInst, %(dest)s, %(add)s, 4566430Sgblack@eecs.umich.edu imm, false); 4576430Sgblack@eecs.umich.edu ''' 4586430Sgblack@eecs.umich.edu instDecode = ''' 4596430Sgblack@eecs.umich.edu case %(opcode)#x: 4606462Sgblack@eecs.umich.edu if (setCc) { 4616430Sgblack@eecs.umich.edu if (%(pclrInst)s && %(dest)s == INTREG_PC) { 4626462Sgblack@eecs.umich.edu %(pclr)s 4636430Sgblack@eecs.umich.edu } else { 4646430Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 4655040Sgblack@eecs.umich.edu imm, rotC); 4666463Sgblack@eecs.umich.edu } 4676463Sgblack@eecs.umich.edu } else { 4686463Sgblack@eecs.umich.edu if (%(adrInst)s && %(op1)s == INTREG_PC) { 4696463Sgblack@eecs.umich.edu %(adr)s 4706463Sgblack@eecs.umich.edu } else { 4716463Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 4726463Sgblack@eecs.umich.edu imm, rotC); 4736463Sgblack@eecs.umich.edu } 4745040Sgblack@eecs.umich.edu } 4755063Sgblack@eecs.umich.edu break; 4765040Sgblack@eecs.umich.edu ''' 4775063Sgblack@eecs.umich.edu 4784809Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 4796742Svince@csl.cornell.edu global instDecode, pclr, adr 4806430Sgblack@eecs.umich.edu if useDest: 4815063Sgblack@eecs.umich.edu dest = "rd" 4826461Sgblack@eecs.umich.edu else: 4835063Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 4845063Sgblack@eecs.umich.edu if useOp1: 4856430Sgblack@eecs.umich.edu op1 = "rn" 4865063Sgblack@eecs.umich.edu else: 4875040Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 4886463Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 4896463Sgblack@eecs.umich.edu "opcode": opcode, 4906463Sgblack@eecs.umich.edu "dest": dest, 4916463Sgblack@eecs.umich.edu "op1": op1, 4926463Sgblack@eecs.umich.edu "adr": "", 4936463Sgblack@eecs.umich.edu "adrInst": "false" } 4946463Sgblack@eecs.umich.edu if useDest: 4955040Sgblack@eecs.umich.edu substDict["pclrInst"] = "true" 4965063Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 4975063Sgblack@eecs.umich.edu else: 4985040Sgblack@eecs.umich.edu substDict["pclrInst"] = "false" 4995063Sgblack@eecs.umich.edu substDict["pclr"] = "" 5005063Sgblack@eecs.umich.edu return instDecode % substDict 5015063Sgblack@eecs.umich.edu 5025063Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 5036345Sgblack@eecs.umich.edu global instDecode, pclr, adr 5046345Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 5055063Sgblack@eecs.umich.edu "opcode": opcode, 5065062Sgblack@eecs.umich.edu "dest": "rd", 5075075Sgblack@eecs.umich.edu "op1": "rn", 5085075Sgblack@eecs.umich.edu "add": add, 5095040Sgblack@eecs.umich.edu "pclrInst": "true", 5105075Sgblack@eecs.umich.edu "adrInst": "true" } 5115075Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 5125075Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 5135075Sgblack@eecs.umich.edu return instDecode % substDict 5145075Sgblack@eecs.umich.edu 5155075Sgblack@eecs.umich.edu decode_block = ''' 5165075Sgblack@eecs.umich.edu { 5175075Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 5185075Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 5195075Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 5207719Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 5217719Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 5227719Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 5237719Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 5247719Sgblack@eecs.umich.edu switch (OPCODE) { 5257719Sgblack@eecs.umich.edu ''' 5267719Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 5277719Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 5287719Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 5295040Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 5304823Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 5315075Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 5325075Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 5335075Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 5345075Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 5355075Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 5365075Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 5375075Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 5385075Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 5395075Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 5405075Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 5417719Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 5427719Sgblack@eecs.umich.edu decode_block += ''' 5437719Sgblack@eecs.umich.edu default: 5447070Sgblack@eecs.umich.edu return new Unknown(machInst); 5457070Sgblack@eecs.umich.edu } 5467070Sgblack@eecs.umich.edu } 5477070Sgblack@eecs.umich.edu ''' 5487070Sgblack@eecs.umich.edu}}; 5497070Sgblack@eecs.umich.edu 5507070Sgblack@eecs.umich.edudef format ArmSatAddSub() {{ 5517070Sgblack@eecs.umich.edu decode_block = ''' 5527080Sgblack@eecs.umich.edu { 5537070Sgblack@eecs.umich.edu IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5547080Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 5557070Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5567070Sgblack@eecs.umich.edu switch (OPCODE) { 5577070Sgblack@eecs.umich.edu case 0x8: 5587070Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 5597070Sgblack@eecs.umich.edu case 0x9: 5607080Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 5617080Sgblack@eecs.umich.edu case 0xa: 5627080Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 5637080Sgblack@eecs.umich.edu case 0xb: 5647070Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 5657070Sgblack@eecs.umich.edu default: 5667070Sgblack@eecs.umich.edu return new Unknown(machInst); 5677070Sgblack@eecs.umich.edu } 5687070Sgblack@eecs.umich.edu } 5697070Sgblack@eecs.umich.edu ''' 5707070Sgblack@eecs.umich.edu}}; 5717070Sgblack@eecs.umich.edu 5727070Sgblack@eecs.umich.edudef format Thumb32DataProcReg() {{ 5737070Sgblack@eecs.umich.edu decode_block = ''' 5747070Sgblack@eecs.umich.edu { 5757070Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 23, 20); 5767070Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5775075Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 4); 5785075Sgblack@eecs.umich.edu if (bits(op1, 3) != 1) { 5795075Sgblack@eecs.umich.edu if (op2 == 0) { 5805075Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5815075Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5825075Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 5835075Sgblack@eecs.umich.edu case 0x0: 5845075Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5855075Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5867480Sgblack@eecs.umich.edu case 0x1: 5875075Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5885075Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5895075Sgblack@eecs.umich.edu case 0x2: 5905075Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5914732Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5925075Sgblack@eecs.umich.edu case 0x3: 5935075Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5945075Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5955075Sgblack@eecs.umich.edu case 0x4: 5965075Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5975040Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 5985040Sgblack@eecs.umich.edu case 0x5: 5995040Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6006482Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6015040Sgblack@eecs.umich.edu case 0x6: 6024732Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 6035040Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6045076Sgblack@eecs.umich.edu case 0x7: 6055040Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6064756Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6074823Sgblack@eecs.umich.edu } 6085040Sgblack@eecs.umich.edu } 6095076Sgblack@eecs.umich.edu { 6105076Sgblack@eecs.umich.edu const IntRegIndex rd = 6115076Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6125076Sgblack@eecs.umich.edu const IntRegIndex rm = 6135076Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6145076Sgblack@eecs.umich.edu const uint32_t rotation = 6155076Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 5, 4) << 3; 6165076Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 6176441Sgblack@eecs.umich.edu case 0x0: 6186441Sgblack@eecs.umich.edu if (rn == 0xf) { 6195076Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 6206441Sgblack@eecs.umich.edu } else { 6215076Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 6225076Sgblack@eecs.umich.edu } 6235076Sgblack@eecs.umich.edu case 0x1: 6245076Sgblack@eecs.umich.edu if (rn == 0xf) { 6255076Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 6265076Sgblack@eecs.umich.edu } else { 6275076Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 6285076Sgblack@eecs.umich.edu } 6295076Sgblack@eecs.umich.edu case 0x2: 6305076Sgblack@eecs.umich.edu if (rn == 0xf) { 6315076Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 6325040Sgblack@eecs.umich.edu } else { 6335076Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 6345040Sgblack@eecs.umich.edu } 6354756Sgblack@eecs.umich.edu case 0x3: 6364732Sgblack@eecs.umich.edu if (rn == 0xf) { 6374732Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 6384732Sgblack@eecs.umich.edu } else { 6394732Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 6404823Sgblack@eecs.umich.edu } 6415040Sgblack@eecs.umich.edu case 0x4: 6425076Sgblack@eecs.umich.edu if (rn == 0xf) { 6435076Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 6445076Sgblack@eecs.umich.edu } else { 6455076Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 6465076Sgblack@eecs.umich.edu } 6475076Sgblack@eecs.umich.edu case 0x5: 6485076Sgblack@eecs.umich.edu if (rn == 0xf) { 6496442Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 6506442Sgblack@eecs.umich.edu } else { 6516442Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 6525076Sgblack@eecs.umich.edu } 6536442Sgblack@eecs.umich.edu default: 6545076Sgblack@eecs.umich.edu return new Unknown(machInst); 6555076Sgblack@eecs.umich.edu } 6565076Sgblack@eecs.umich.edu } 6575076Sgblack@eecs.umich.edu } else { 6585076Sgblack@eecs.umich.edu if (bits(op2, 3) == 0) { 6595076Sgblack@eecs.umich.edu const IntRegIndex rd = 6605076Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6615076Sgblack@eecs.umich.edu const IntRegIndex rm = 6625040Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6635076Sgblack@eecs.umich.edu if (bits(op2, 2) == 0x0) { 6645040Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 6654756Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 6664732Sgblack@eecs.umich.edu switch (op2) { 6674732Sgblack@eecs.umich.edu case 0x0: 6684732Sgblack@eecs.umich.edu switch (op1) { 6696443Sgblack@eecs.umich.edu case 0x1: 6705032Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, 6714823Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6725040Sgblack@eecs.umich.edu case 0x2: 6735076Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, 6745076Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6755076Sgblack@eecs.umich.edu case 0x6: 6765076Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, 6775076Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6785076Sgblack@eecs.umich.edu case 0x5: 6795076Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, 6806444Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6816444Sgblack@eecs.umich.edu case 0x0: 6826444Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, 6836444Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6845076Sgblack@eecs.umich.edu case 0x4: 6856444Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, 6865076Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6875076Sgblack@eecs.umich.edu } 6885076Sgblack@eecs.umich.edu break; 6895076Sgblack@eecs.umich.edu case 0x1: 6905076Sgblack@eecs.umich.edu switch (op1) { 6915040Sgblack@eecs.umich.edu case 0x1: 6925076Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 6935040Sgblack@eecs.umich.edu case 0x2: 6944732Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 6954756Sgblack@eecs.umich.edu case 0x6: 6966449Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 6976449Sgblack@eecs.umich.edu case 0x5: 6984732Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 6996449Sgblack@eecs.umich.edu case 0x0: 7006449Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 7014732Sgblack@eecs.umich.edu case 0x4: 7024732Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 7034732Sgblack@eecs.umich.edu } 7046447Sgblack@eecs.umich.edu break; 7055040Sgblack@eecs.umich.edu case 0x2: 7065076Sgblack@eecs.umich.edu switch (op1) { 7075076Sgblack@eecs.umich.edu case 0x1: 7085076Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 7095076Sgblack@eecs.umich.edu case 0x2: 7105076Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 7115076Sgblack@eecs.umich.edu case 0x6: 7125076Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 7135076Sgblack@eecs.umich.edu case 0x5: 7145076Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 7155076Sgblack@eecs.umich.edu case 0x0: 7165076Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 7175076Sgblack@eecs.umich.edu case 0x4: 7185076Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 7195076Sgblack@eecs.umich.edu } 7205076Sgblack@eecs.umich.edu break; 7215076Sgblack@eecs.umich.edu } 7225076Sgblack@eecs.umich.edu } else { 7235076Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 7245076Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7255076Sgblack@eecs.umich.edu switch (op2) { 7265040Sgblack@eecs.umich.edu case 0x0: 7275076Sgblack@eecs.umich.edu switch (op1) { 7285040Sgblack@eecs.umich.edu case 0x1: 7294733Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, 7304756Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7316454Sgblack@eecs.umich.edu case 0x2: 7326454Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, 7334733Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7344733Sgblack@eecs.umich.edu case 0x6: 7356454Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, 7366454Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7376454Sgblack@eecs.umich.edu case 0x5: 7386454Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, 7394733Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7404733Sgblack@eecs.umich.edu case 0x0: 7414733Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, 7426447Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7435040Sgblack@eecs.umich.edu case 0x4: 7445076Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, 7455076Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7465076Sgblack@eecs.umich.edu } 7476453Sgblack@eecs.umich.edu break; 7485076Sgblack@eecs.umich.edu case 0x1: 7495076Sgblack@eecs.umich.edu switch (op1) { 7505076Sgblack@eecs.umich.edu case 0x1: 7515076Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 7526453Sgblack@eecs.umich.edu case 0x2: 7536453Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 7545076Sgblack@eecs.umich.edu case 0x6: 7556453Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 7565076Sgblack@eecs.umich.edu case 0x5: 7576454Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 7586454Sgblack@eecs.umich.edu case 0x0: 7596454Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 7605076Sgblack@eecs.umich.edu case 0x4: 7616454Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 7625076Sgblack@eecs.umich.edu } 7635076Sgblack@eecs.umich.edu break; 7645076Sgblack@eecs.umich.edu case 0x2: 7655076Sgblack@eecs.umich.edu switch (op1) { 7665076Sgblack@eecs.umich.edu case 0x1: 7675040Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 7685076Sgblack@eecs.umich.edu case 0x2: 7695040Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 7704732Sgblack@eecs.umich.edu case 0x6: 7714756Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 7726446Sgblack@eecs.umich.edu case 0x5: 7736446Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 7744732Sgblack@eecs.umich.edu case 0x0: 7756446Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 7764732Sgblack@eecs.umich.edu case 0x4: 7776446Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 7784732Sgblack@eecs.umich.edu } 7794732Sgblack@eecs.umich.edu break; 7804732Sgblack@eecs.umich.edu } 7816447Sgblack@eecs.umich.edu } 7825040Sgblack@eecs.umich.edu } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 7835076Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 7845076Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7855076Sgblack@eecs.umich.edu const IntRegIndex rd = 7865076Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7875076Sgblack@eecs.umich.edu const IntRegIndex rm = 7885076Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 7895076Sgblack@eecs.umich.edu switch (op1) { 7905076Sgblack@eecs.umich.edu case 0x0: 7915076Sgblack@eecs.umich.edu switch (op2) { 7925076Sgblack@eecs.umich.edu case 0x0: 7935076Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, 7945076Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7955076Sgblack@eecs.umich.edu case 0x1: 7965076Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, 7975076Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7985076Sgblack@eecs.umich.edu case 0x2: 7995076Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, 8005076Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8015076Sgblack@eecs.umich.edu case 0x3: 8025076Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, 8035040Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8045076Sgblack@eecs.umich.edu } 8055040Sgblack@eecs.umich.edu break; 8064733Sgblack@eecs.umich.edu case 0x1: 8074756Sgblack@eecs.umich.edu switch (op2) { 8086456Sgblack@eecs.umich.edu case 0x0: 8096456Sgblack@eecs.umich.edu return new Rev(machInst, rd, rn); 8104733Sgblack@eecs.umich.edu case 0x1: 8114733Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rn); 8126456Sgblack@eecs.umich.edu case 0x2: 8136456Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 8144733Sgblack@eecs.umich.edu case 0x3: 8154733Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rn); 8164823Sgblack@eecs.umich.edu } 8176456Sgblack@eecs.umich.edu break; 8184733Sgblack@eecs.umich.edu case 0x2: 8194733Sgblack@eecs.umich.edu if (op2 == 0) { 8204733Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 8216447Sgblack@eecs.umich.edu } 8225040Sgblack@eecs.umich.edu break; 8235076Sgblack@eecs.umich.edu case 0x3: 8245076Sgblack@eecs.umich.edu if (op2 == 0) { 8255076Sgblack@eecs.umich.edu return new Clz(machInst, rd, rm); 8266456Sgblack@eecs.umich.edu } 8275076Sgblack@eecs.umich.edu } 8285076Sgblack@eecs.umich.edu } 8295076Sgblack@eecs.umich.edu return new Unknown(machInst); 8305076Sgblack@eecs.umich.edu } 8316456Sgblack@eecs.umich.edu } 8325076Sgblack@eecs.umich.edu ''' 8336456Sgblack@eecs.umich.edu}}; 8346456Sgblack@eecs.umich.edu 8355076Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 8365076Sgblack@eecs.umich.edu decode_block = ''' 8375076Sgblack@eecs.umich.edu { 8385076Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 8395076Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 8405076Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 8415076Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8425076Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 8435076Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8444732Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 8456479Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 8466479Sgblack@eecs.umich.edu case 0x0: // lsl 8476479Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8486479Sgblack@eecs.umich.edu case 0x1: // lsr 8496479Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8506479Sgblack@eecs.umich.edu case 0x2: // asr 8516479Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8526479Sgblack@eecs.umich.edu case 0x3: 8536479Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 8546479Sgblack@eecs.umich.edu case 0x0: 8556479Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 8566479Sgblack@eecs.umich.edu case 0x1: 8576479Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 8586479Sgblack@eecs.umich.edu case 0x2: 8596479Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 8606479Sgblack@eecs.umich.edu case 0x3: 8616479Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 8626479Sgblack@eecs.umich.edu } 8636479Sgblack@eecs.umich.edu case 0x4: 8646479Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 8656479Sgblack@eecs.umich.edu case 0x5: 8666479Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 8676479Sgblack@eecs.umich.edu case 0x6: 8686479Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 8696479Sgblack@eecs.umich.edu case 0x7: 8706479Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 8716479Sgblack@eecs.umich.edu } 8726479Sgblack@eecs.umich.edu } 8736479Sgblack@eecs.umich.edu ''' 8746479Sgblack@eecs.umich.edu}}; 8756479Sgblack@eecs.umich.edu 8766479Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 8776479Sgblack@eecs.umich.edu decode_block = ''' 8786479Sgblack@eecs.umich.edu { 8796479Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8806479Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8816479Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 8826479Sgblack@eecs.umich.edu case 0x0: 8836479Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 8846479Sgblack@eecs.umich.edu case 0x1: 8856479Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 8866479Sgblack@eecs.umich.edu case 0x2: //lsl 8876479Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 8886479Sgblack@eecs.umich.edu case 0x3: //lsr 8896479Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 8906479Sgblack@eecs.umich.edu case 0x4: //asr 8916479Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 8926479Sgblack@eecs.umich.edu case 0x5: 8936479Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 8946479Sgblack@eecs.umich.edu case 0x6: 8956479Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 8966479Sgblack@eecs.umich.edu case 0x7: // ror 8976479Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 8986479Sgblack@eecs.umich.edu case 0x8: 8996479Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9006479Sgblack@eecs.umich.edu case 0x9: 9016479Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 9026479Sgblack@eecs.umich.edu case 0xa: 9036479Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9046479Sgblack@eecs.umich.edu case 0xb: 9056479Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9066479Sgblack@eecs.umich.edu case 0xc: 9076479Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 9086479Sgblack@eecs.umich.edu case 0xd: 9096479Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 9106479Sgblack@eecs.umich.edu case 0xe: 9116479Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 9126479Sgblack@eecs.umich.edu case 0xf: 9136479Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 9146479Sgblack@eecs.umich.edu } 9156479Sgblack@eecs.umich.edu } 9166479Sgblack@eecs.umich.edu ''' 9176479Sgblack@eecs.umich.edu}}; 9186479Sgblack@eecs.umich.edu 9196479Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 9206479Sgblack@eecs.umich.edu decode_block = ''' 9216479Sgblack@eecs.umich.edu { 9226479Sgblack@eecs.umich.edu const IntRegIndex rdn = 9236479Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 9246479Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 9256479Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 9266479Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 9276479Sgblack@eecs.umich.edu case 0x0: 9286479Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 9296479Sgblack@eecs.umich.edu case 0x1: 9306479Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9316479Sgblack@eecs.umich.edu case 0x2: 9326479Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 9336479Sgblack@eecs.umich.edu case 0x3: 9346479Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 9356479Sgblack@eecs.umich.edu return new BxReg(machInst, 9366479Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9376479Sgblack@eecs.umich.edu COND_UC); 9386479Sgblack@eecs.umich.edu } else { 9396479Sgblack@eecs.umich.edu return new BlxReg(machInst, 9406479Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9416479Sgblack@eecs.umich.edu COND_UC); 9426479Sgblack@eecs.umich.edu } 9436479Sgblack@eecs.umich.edu } 9446479Sgblack@eecs.umich.edu } 9456479Sgblack@eecs.umich.edu ''' 9465040Sgblack@eecs.umich.edu}}; 9477789Sgblack@eecs.umich.edu 9487789Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 9495040Sgblack@eecs.umich.edu decode_block = ''' 9505040Sgblack@eecs.umich.edu { 9515040Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9525040Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9535426Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 9545426Sgblack@eecs.umich.edu } 9555426Sgblack@eecs.umich.edu ''' 9565426Sgblack@eecs.umich.edu}}; 9575426Sgblack@eecs.umich.edu 9585426Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 9595426Sgblack@eecs.umich.edu decode_block = ''' 9605426Sgblack@eecs.umich.edu { 9615426Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9625426Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9635040Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 9647789Sgblack@eecs.umich.edu } 9655040Sgblack@eecs.umich.edu ''' 9665040Sgblack@eecs.umich.edu}}; 9675040Sgblack@eecs.umich.edu 9685040Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 9695426Sgblack@eecs.umich.edu decode_block = ''' 9705426Sgblack@eecs.umich.edu { 9715426Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 9725040Sgblack@eecs.umich.edu case 0x0: 9735040Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 9745116Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 9754951Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9765011Sgblack@eecs.umich.edu } else { 9775011Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 9785040Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9795040Sgblack@eecs.umich.edu } 9805040Sgblack@eecs.umich.edu case 0x1: 9815040Sgblack@eecs.umich.edu return new Cbz(machInst, 9826345Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 9834732Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 9845426Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 9855426Sgblack@eecs.umich.edu case 0x2: 9865426Sgblack@eecs.umich.edu { 9875426Sgblack@eecs.umich.edu const IntRegIndex rd = 9885426Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 9895426Sgblack@eecs.umich.edu const IntRegIndex rm = 9905426Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 9915426Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 9925426Sgblack@eecs.umich.edu case 0x0: 9935426Sgblack@eecs.umich.edu return new Sxth(machInst, rd, 0, rm); 9945426Sgblack@eecs.umich.edu case 0x1: 9955426Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, 0, rm); 9966345Sgblack@eecs.umich.edu case 0x2: 9975426Sgblack@eecs.umich.edu return new Uxth(machInst, rd, 0, rm); 9985040Sgblack@eecs.umich.edu case 0x3: 9995040Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, 0, rm); 10004823Sgblack@eecs.umich.edu } 10015239Sgblack@eecs.umich.edu } 10025239Sgblack@eecs.umich.edu case 0x3: 10035239Sgblack@eecs.umich.edu return new Cbz(machInst, 10045239Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10055007Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10065007Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10075040Sgblack@eecs.umich.edu case 0x4: 10085239Sgblack@eecs.umich.edu case 0x5: 10095239Sgblack@eecs.umich.edu { 10105239Sgblack@eecs.umich.edu const uint32_t m = bits(machInst, 8); 10115239Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 10125239Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, false, false, false, 10135239Sgblack@eecs.umich.edu true, false, regList); 10145239Sgblack@eecs.umich.edu } 10155239Sgblack@eecs.umich.edu case 0x6: 10164714Sgblack@eecs.umich.edu { 10175040Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 10185927Sgblack@eecs.umich.edu if (opBits == 2) { 10195241Sgblack@eecs.umich.edu return new WarnUnimplemented("setend", machInst); 10205926Sgblack@eecs.umich.edu } else if (opBits == 3) { 10215926Sgblack@eecs.umich.edu return new WarnUnimplemented("cps", machInst); 10225926Sgblack@eecs.umich.edu } 10236345Sgblack@eecs.umich.edu } 10245926Sgblack@eecs.umich.edu case 0x9: 10255926Sgblack@eecs.umich.edu return new Cbnz(machInst, 10265926Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10275926Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10285926Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10295926Sgblack@eecs.umich.edu case 0xa: 10305926Sgblack@eecs.umich.edu { 10315926Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 10325926Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 10335926Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 10345926Sgblack@eecs.umich.edu case 0x0: 10355926Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 10365926Sgblack@eecs.umich.edu case 0x1: 10375926Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 10385926Sgblack@eecs.umich.edu case 0x3: 10396345Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 10405926Sgblack@eecs.umich.edu default: 10415926Sgblack@eecs.umich.edu break; 10425926Sgblack@eecs.umich.edu } 10435926Sgblack@eecs.umich.edu } 10445926Sgblack@eecs.umich.edu break; 10456345Sgblack@eecs.umich.edu case 0xb: 10465926Sgblack@eecs.umich.edu return new Cbnz(machInst, 10475926Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10485926Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10495926Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10505926Sgblack@eecs.umich.edu case 0xc: 10515926Sgblack@eecs.umich.edu case 0xd: 10525926Sgblack@eecs.umich.edu { 10535926Sgblack@eecs.umich.edu const uint32_t p = bits(machInst, 8); 10545926Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 10555296Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, true, true, false, 10565296Sgblack@eecs.umich.edu true, true, regList); 10575296Sgblack@eecs.umich.edu } 10586345Sgblack@eecs.umich.edu case 0xe: 10595296Sgblack@eecs.umich.edu return new WarnUnimplemented("bkpt", machInst); 10605924Sgblack@eecs.umich.edu case 0xf: 10615296Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 10625296Sgblack@eecs.umich.edu return new WarnUnimplemented("it", machInst); 10635934Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 10645296Sgblack@eecs.umich.edu case 0x0: 10655296Sgblack@eecs.umich.edu return new NopInst(machInst); 10665296Sgblack@eecs.umich.edu case 0x1: 10675241Sgblack@eecs.umich.edu return new WarnUnimplemented("yield", machInst); 10685241Sgblack@eecs.umich.edu case 0x2: 10695241Sgblack@eecs.umich.edu return new WarnUnimplemented("wfe", machInst); 10706345Sgblack@eecs.umich.edu case 0x3: 10715241Sgblack@eecs.umich.edu return new WarnUnimplemented("wfi", machInst); 10725241Sgblack@eecs.umich.edu case 0x4: 10735241Sgblack@eecs.umich.edu return new WarnUnimplemented("sev", machInst); 10745241Sgblack@eecs.umich.edu default: 10755241Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 10765241Sgblack@eecs.umich.edu } 10775241Sgblack@eecs.umich.edu default: 10785241Sgblack@eecs.umich.edu break; 10795241Sgblack@eecs.umich.edu } 10805241Sgblack@eecs.umich.edu return new Unknown(machInst); 10815241Sgblack@eecs.umich.edu } 10825241Sgblack@eecs.umich.edu ''' 10835241Sgblack@eecs.umich.edu}}; 10845241Sgblack@eecs.umich.edu 10855241Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 10865241Sgblack@eecs.umich.edu 10875241Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 10885241Sgblack@eecs.umich.edu return ''' 10895241Sgblack@eecs.umich.edu if (s) { 10905241Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 10915241Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10925241Sgblack@eecs.umich.edu } else { 10935241Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 10945241Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10955241Sgblack@eecs.umich.edu } 10965241Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 10975241Sgblack@eecs.umich.edu 10985241Sgblack@eecs.umich.edu decode_block = ''' 10995241Sgblack@eecs.umich.edu { 11005241Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 11015241Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 11025241Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 11035241Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 11045241Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 11055241Sgblack@eecs.umich.edu bits(machInst, 14, 12); 11065241Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 11075241Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 11085241Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 11095241Sgblack@eecs.umich.edu switch (op) { 11105241Sgblack@eecs.umich.edu case 0x0: 11115241Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11125241Sgblack@eecs.umich.edu %(tst)s 11135241Sgblack@eecs.umich.edu } else { 11145241Sgblack@eecs.umich.edu %(and)s 11155241Sgblack@eecs.umich.edu } 11165241Sgblack@eecs.umich.edu case 0x1: 11175241Sgblack@eecs.umich.edu %(bic)s 11185290Sgblack@eecs.umich.edu case 0x2: 11195294Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 11205672Sgblack@eecs.umich.edu %(mov)s 11215294Sgblack@eecs.umich.edu } else { 11225290Sgblack@eecs.umich.edu %(orr)s 11235294Sgblack@eecs.umich.edu } 11246345Sgblack@eecs.umich.edu case 0x3: 11255294Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 11265294Sgblack@eecs.umich.edu %(mvn)s 11275290Sgblack@eecs.umich.edu } else { 11285294Sgblack@eecs.umich.edu %(orn)s 11295290Sgblack@eecs.umich.edu } 11305290Sgblack@eecs.umich.edu case 0x4: 11315294Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11325290Sgblack@eecs.umich.edu %(teq)s 11335294Sgblack@eecs.umich.edu } else { 11345294Sgblack@eecs.umich.edu %(eor)s 11355294Sgblack@eecs.umich.edu } 11365294Sgblack@eecs.umich.edu case 0x8: 11375294Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11385294Sgblack@eecs.umich.edu %(cmn)s 11395294Sgblack@eecs.umich.edu } else { 11405294Sgblack@eecs.umich.edu %(add)s 11415905Sgblack@eecs.umich.edu } 11425905Sgblack@eecs.umich.edu case 0xa: 11435905Sgblack@eecs.umich.edu %(adc)s 11445905Sgblack@eecs.umich.edu case 0xb: 11455905Sgblack@eecs.umich.edu %(sbc)s 11465294Sgblack@eecs.umich.edu case 0xd: 11475294Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11485932Sgblack@eecs.umich.edu %(cmp)s 11495294Sgblack@eecs.umich.edu } else { 11505294Sgblack@eecs.umich.edu %(sub)s 11515294Sgblack@eecs.umich.edu } 11525294Sgblack@eecs.umich.edu case 0xe: 11535932Sgblack@eecs.umich.edu %(rsb)s 11545294Sgblack@eecs.umich.edu default: 11555294Sgblack@eecs.umich.edu return new Unknown(machInst); 11565427Sgblack@eecs.umich.edu } 11575427Sgblack@eecs.umich.edu } 11585932Sgblack@eecs.umich.edu ''' % { 11595427Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 11605427Sgblack@eecs.umich.edu "and" : decInst("And"), 11615294Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 11625294Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 11635932Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 11645294Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 11655294Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 11665682Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 11675682Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 11686345Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 11696345Sgblack@eecs.umich.edu "add" : decInst("Add"), 11705682Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 11715682Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 11725682Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 11735682Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 11745682Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 11755682Sgblack@eecs.umich.edu } 11766345Sgblack@eecs.umich.edu}}; 11776345Sgblack@eecs.umich.edu 11785682Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 11795682Sgblack@eecs.umich.edu decode_block = ''' 11805682Sgblack@eecs.umich.edu { 11815682Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 11825428Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 11835428Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 11845428Sgblack@eecs.umich.edu switch (op) { 11855428Sgblack@eecs.umich.edu case 0x0: 11865428Sgblack@eecs.umich.edu { 11875294Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 11885424Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 11895433Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 11905433Sgblack@eecs.umich.edu if (rn == 0xf) { 11915433Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 11925294Sgblack@eecs.umich.edu imm, false); 11935428Sgblack@eecs.umich.edu } else { 11945428Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 11955428Sgblack@eecs.umich.edu } 11965428Sgblack@eecs.umich.edu } 11975428Sgblack@eecs.umich.edu case 0x4: 11986060Sgblack@eecs.umich.edu { 11996060Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12006060Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12016060Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 12026060Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 12036060Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 12045428Sgblack@eecs.umich.edu } 12055428Sgblack@eecs.umich.edu case 0xa: 12065428Sgblack@eecs.umich.edu { 12075428Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12085428Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12095855Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 12105853Sgblack@eecs.umich.edu if (rn == 0xf) { 12115674Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 12125857Sgblack@eecs.umich.edu imm, false); 12136058Sgblack@eecs.umich.edu } else { 12145674Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 12155855Sgblack@eecs.umich.edu } 12165855Sgblack@eecs.umich.edu } 12175853Sgblack@eecs.umich.edu case 0xc: 12185861Snate@binkert.org { 12195853Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12205853Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12215853Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 12225674Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 12235428Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 12245433Sgblack@eecs.umich.edu } 12255433Sgblack@eecs.umich.edu case 0x12: 12265857Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 12275433Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12285433Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 12295673Sgblack@eecs.umich.edu } 12305673Sgblack@eecs.umich.edu // Fall through on purpose... 12315433Sgblack@eecs.umich.edu case 0x10: 12325433Sgblack@eecs.umich.edu { 12335433Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12345433Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12355857Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12365433Sgblack@eecs.umich.edu const ArmShiftType type = 12375433Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12385428Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 12395428Sgblack@eecs.umich.edu } 12405428Sgblack@eecs.umich.edu case 0x14: 12415433Sgblack@eecs.umich.edu return new WarnUnimplemented("sbfx", machInst); 12425433Sgblack@eecs.umich.edu case 0x16: 12435433Sgblack@eecs.umich.edu if (rn == 0xf) { 12445433Sgblack@eecs.umich.edu return new WarnUnimplemented("bfc", machInst); 12455679Sgblack@eecs.umich.edu } else { 12465857Sgblack@eecs.umich.edu return new WarnUnimplemented("bfi", machInst); 12475679Sgblack@eecs.umich.edu } 12485857Sgblack@eecs.umich.edu case 0x1a: 12495679Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 12505428Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12515428Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 12525428Sgblack@eecs.umich.edu } 12535675Sgblack@eecs.umich.edu // Fall through on purpose... 12545675Sgblack@eecs.umich.edu case 0x18: 12555679Sgblack@eecs.umich.edu { 12565675Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12575675Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12585675Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12595675Sgblack@eecs.umich.edu const ArmShiftType type = 12605675Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12615428Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 12625899Sgblack@eecs.umich.edu } 12635899Sgblack@eecs.umich.edu case 0x1c: 12645899Sgblack@eecs.umich.edu return new WarnUnimplemented("ubfx", machInst); 12655899Sgblack@eecs.umich.edu default: 12665899Sgblack@eecs.umich.edu return new Unknown(machInst); 12675900Sgblack@eecs.umich.edu } 12685900Sgblack@eecs.umich.edu } 12695900Sgblack@eecs.umich.edu ''' 12705900Sgblack@eecs.umich.edu}}; 12715900Sgblack@eecs.umich.edu 12725900Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 12735935Sgblack@eecs.umich.edu 12745900Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 12755900Sgblack@eecs.umich.edu return ''' 12765936Sgblack@eecs.umich.edu if (s) { 12775936Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 12785936Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 12795936Sgblack@eecs.umich.edu } else { 12805936Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 12815936Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 12825936Sgblack@eecs.umich.edu } 12835936Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 12845936Sgblack@eecs.umich.edu 12855936Sgblack@eecs.umich.edu decode_block = ''' 12865936Sgblack@eecs.umich.edu { 12875936Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 12885428Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 12895428Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 12905428Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 12915294Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 12925294Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 12935294Sgblack@eecs.umich.edu bits(machInst, 7, 6); 12945294Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 12955424Sgblack@eecs.umich.edu switch (op) { 12965294Sgblack@eecs.umich.edu case 0x0: 12975294Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 12985294Sgblack@eecs.umich.edu %(tst)s 12995294Sgblack@eecs.umich.edu } else { 13005294Sgblack@eecs.umich.edu %(and)s 13015678Sgblack@eecs.umich.edu } 13025294Sgblack@eecs.umich.edu case 0x1: 13035678Sgblack@eecs.umich.edu %(bic)s 13045678Sgblack@eecs.umich.edu case 0x2: 13055678Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13065678Sgblack@eecs.umich.edu %(mov)s 13075678Sgblack@eecs.umich.edu } else { 13085678Sgblack@eecs.umich.edu %(orr)s 13095678Sgblack@eecs.umich.edu } 13105678Sgblack@eecs.umich.edu case 0x3: 13115678Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13125678Sgblack@eecs.umich.edu %(mvn)s 13135678Sgblack@eecs.umich.edu } else { 13145678Sgblack@eecs.umich.edu %(orn)s 13155678Sgblack@eecs.umich.edu } 13165678Sgblack@eecs.umich.edu case 0x4: 13175678Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13185678Sgblack@eecs.umich.edu %(teq)s 13195678Sgblack@eecs.umich.edu } else { 13205678Sgblack@eecs.umich.edu %(eor)s 13215294Sgblack@eecs.umich.edu } 13225294Sgblack@eecs.umich.edu case 0x6: 13235409Sgblack@eecs.umich.edu if (type) { 13245409Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, rn, rm, amt, type); 13255409Sgblack@eecs.umich.edu } else { 13265409Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, rn, rm, amt, type); 13275409Sgblack@eecs.umich.edu } 13285409Sgblack@eecs.umich.edu case 0x8: 13295409Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13305409Sgblack@eecs.umich.edu %(cmn)s 13315409Sgblack@eecs.umich.edu } else { 13325409Sgblack@eecs.umich.edu %(add)s 13335429Sgblack@eecs.umich.edu } 13345429Sgblack@eecs.umich.edu case 0xa: 13355429Sgblack@eecs.umich.edu %(adc)s 13365429Sgblack@eecs.umich.edu case 0xb: 13375429Sgblack@eecs.umich.edu %(sbc)s 13385294Sgblack@eecs.umich.edu case 0xd: 13395294Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13405294Sgblack@eecs.umich.edu %(cmp)s 13415433Sgblack@eecs.umich.edu } else { 13425433Sgblack@eecs.umich.edu %(sub)s 13436222Sgblack@eecs.umich.edu } 13446222Sgblack@eecs.umich.edu case 0xe: 13455433Sgblack@eecs.umich.edu %(rsb)s 13465433Sgblack@eecs.umich.edu default: 13476222Sgblack@eecs.umich.edu return new Unknown(machInst); 13485433Sgblack@eecs.umich.edu } 13496222Sgblack@eecs.umich.edu } 13506222Sgblack@eecs.umich.edu ''' % { 13516222Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 13526222Sgblack@eecs.umich.edu "and" : decInst("And"), 13536222Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 13546222Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 13555433Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 13565901Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 13575901Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 13585901Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 13595901Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 13605901Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 13615901Sgblack@eecs.umich.edu "add" : decInst("Add"), 13626222Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 13635433Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 13645433Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 13656222Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 13665433Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 13676222Sgblack@eecs.umich.edu } 13685433Sgblack@eecs.umich.edu}}; 13695433Sgblack@eecs.umich.edu