breakpoint.isa revision 12616:4b463b4dc098
12SN/A// -*- mode:c++ -*-
211071SN/A
311071SN/A// Copyright (c) 2010,2018 ARM Limited
411071SN/A// All rights reserved
511071SN/A//
611071SN/A// The license below extends only to copyright in the software and shall
711071SN/A// not be construed as granting a license to any other intellectual
811071SN/A// property including but not limited to intellectual property relating
911071SN/A// to a hardware implementation of the functionality of the software
1011071SN/A// licensed hereunder.  You may use the software subject to the license
1111071SN/A// terms below provided that you ensure that this notice is replicated
1211071SN/A// unmodified and in its entirety in all distributions of the software,
1311071SN/A// modified or unmodified, in source code or in binary form.
141762SN/A//
152SN/A// Copyright (c) 2007-2008 The Florida State University
162SN/A// All rights reserved.
172SN/A//
182SN/A// Redistribution and use in source and binary forms, with or without
192SN/A// modification, are permitted provided that the following conditions are
202SN/A// met: redistributions of source code must retain the above copyright
212SN/A// notice, this list of conditions and the following disclaimer;
222SN/A// redistributions in binary form must reproduce the above copyright
232SN/A// notice, this list of conditions and the following disclaimer in the
242SN/A// documentation and/or other materials provided with the distribution;
252SN/A// neither the name of the copyright holders nor the names of its
262SN/A// contributors may be used to endorse or promote products derived from
272SN/A// this software without specific prior written permission.
282SN/A//
292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392665SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402665SN/A//
412SN/A// Authors: Stephen Hines
422SN/A
432SN/A////////////////////////////////////////////////////////////////////
442SN/A//
452SN/A// Breakpoint instructions
462SN/A//
4711263Sandreas.sandberg@arm.com
4811263Sandreas.sandberg@arm.comoutput header {{
492SN/A    /**
5011071SN/A     * Static instruction class for Breakpoint (illegal) instructions.
5111071SN/A     * These cause simulator termination if they are executed in a
526216SN/A     * non-speculative mode.  This is a leaf class.
5311263Sandreas.sandberg@arm.com     */
5411263Sandreas.sandberg@arm.com    class Breakpoint : public ArmStaticInst
554981SN/A    {
561354SN/A      public:
5756SN/A        /// Constructor
582SN/A        Breakpoint(ExtMachInst _machInst)
592SN/A            : ArmStaticInst("Breakpoint", _machInst, No_OpClass)
601435SN/A        {
612SN/A            // don't call execute() (which panics) if we're on a
622SN/A            // speculative path
632SN/A            flags[IsNonSpeculative] = true;
6413784Sgabeblack@google.com        }
652SN/A
662SN/A        Fault execute(ExecContext *, Trace::InstRecord *) const override;
672SN/A
682SN/A        std::string
6911071SN/A        generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
7011071SN/A    };
7111071SN/A}};
721435SN/A
731435SN/Aoutput decoder {{
742SN/A    std::string
7511071SN/A    Breakpoint::generateDisassembly(Addr pc, const SymbolTable *symtab) const
76265SN/A    {
7711071SN/A        return csprintf("%-10s (inst 0x%x)", "Breakpoint", machInst);
7811071SN/A    }
791435SN/A}};
802SN/A
812SN/Aoutput exec {{
822SN/A    Fault
8311071SN/A    Breakpoint::execute(ExecContext *xc, Trace::InstRecord *traceData) const
8411071SN/A    {
8511071SN/A        return std::make_shared<PrefetchAbort>(xc->pcState().pc(),
8611071SN/A                                               ArmFault::DebugEvent);
872SN/A    }
882SN/A}};
892SN/A
902SN/Adef format ArmBkptHlt() {{
912SN/A    decode_block = '''
922566SN/A    {
93633SN/A        if (bits(machInst, 21)) {
9412087Sspwilson2@wisc.edu            return new Breakpoint(machInst);
952SN/A        } else {
9611071SN/A            uint32_t imm16 = (bits(machInst, 19, 8) << 4) |
9711071SN/A                             (bits(machInst,  3, 0) << 0);
9811071SN/A            return new Hlt(machInst, imm16);
9911071SN/A        }
10011071SN/A    }
10111071SN/A    '''
10211071SN/A}};
10311071SN/A
10412087Sspwilson2@wisc.edu