aarch64.isa revision 12714:6870e0c151b1
1// Copyright (c) 2011-2018 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Gabe Black 37// Thomas Grocutt 38// Mbou Eyole 39// Giacomo Gabrielli 40 41output header {{ 42namespace Aarch64 43{ 44 StaticInstPtr decodeDataProcImm(ExtMachInst machInst); 45 StaticInstPtr decodeBranchExcSys(ExtMachInst machInst); 46 StaticInstPtr decodeLoadsStores(ExtMachInst machInst); 47 StaticInstPtr decodeDataProcReg(ExtMachInst machInst); 48 49 template <typename DecoderFeatures> 50 StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); 51 StaticInstPtr decodeFp(ExtMachInst machInst); 52 template <typename DecoderFeatures> 53 StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); 54 StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); 55 56 StaticInstPtr decodeGem5Ops(ExtMachInst machInst); 57} 58}}; 59 60output decoder {{ 61namespace Aarch64 62{ 63 StaticInstPtr 64 decodeDataProcImm(ExtMachInst machInst) 65 { 66 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 67 IntRegIndex rdsp = makeSP(rd); 68 IntRegIndex rdzr = makeZero(rd); 69 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 70 IntRegIndex rnsp = makeSP(rn); 71 72 uint8_t opc = bits(machInst, 30, 29); 73 bool sf = bits(machInst, 31); 74 bool n = bits(machInst, 22); 75 uint8_t immr = bits(machInst, 21, 16); 76 uint8_t imms = bits(machInst, 15, 10); 77 switch (bits(machInst, 25, 23)) { 78 case 0x0: 79 case 0x1: 80 { 81 uint64_t immlo = bits(machInst, 30, 29); 82 uint64_t immhi = bits(machInst, 23, 5); 83 uint64_t imm = (immlo << 0) | (immhi << 2); 84 if (bits(machInst, 31) == 0) 85 return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm)); 86 else 87 return new AdrpXImm(machInst, rdzr, INTREG_ZERO, 88 sext<33>(imm << 12)); 89 } 90 case 0x2: 91 case 0x3: 92 { 93 uint32_t imm12 = bits(machInst, 21, 10); 94 uint8_t shift = bits(machInst, 23, 22); 95 uint32_t imm; 96 if (shift == 0x0) 97 imm = imm12 << 0; 98 else if (shift == 0x1) 99 imm = imm12 << 12; 100 else 101 return new Unknown64(machInst); 102 switch (opc) { 103 case 0x0: 104 return new AddXImm(machInst, rdsp, rnsp, imm); 105 case 0x1: 106 return new AddXImmCc(machInst, rdzr, rnsp, imm); 107 case 0x2: 108 return new SubXImm(machInst, rdsp, rnsp, imm); 109 case 0x3: 110 return new SubXImmCc(machInst, rdzr, rnsp, imm); 111 default: 112 M5_UNREACHABLE; 113 } 114 } 115 case 0x4: 116 { 117 if (!sf && n) 118 return new Unknown64(machInst); 119 // len = MSB(n:NOT(imms)), len < 1 is undefined. 120 uint8_t len = 0; 121 if (n) { 122 len = 6; 123 } else if (imms == 0x3f || imms == 0x3e) { 124 return new Unknown64(machInst); 125 } else { 126 len = findMsbSet(imms ^ 0x3f); 127 } 128 // Generate r, s, and size. 129 uint64_t r = bits(immr, len - 1, 0); 130 uint64_t s = bits(imms, len - 1, 0); 131 uint8_t size = 1 << len; 132 if (s == size - 1) 133 return new Unknown64(machInst); 134 // Generate the pattern with s 1s, rotated by r, with size bits. 135 uint64_t pattern = mask(s + 1); 136 if (r) { 137 pattern = (pattern >> r) | (pattern << (size - r)); 138 pattern &= mask(size); 139 } 140 uint8_t width = sf ? 64 : 32; 141 // Replicate that to fill up the immediate. 142 for (unsigned i = 1; i < (width / size); i *= 2) 143 pattern |= (pattern << (i * size)); 144 uint64_t imm = pattern; 145 146 switch (opc) { 147 case 0x0: 148 return new AndXImm(machInst, rdsp, rn, imm); 149 case 0x1: 150 return new OrrXImm(machInst, rdsp, rn, imm); 151 case 0x2: 152 return new EorXImm(machInst, rdsp, rn, imm); 153 case 0x3: 154 return new AndXImmCc(machInst, rdzr, rn, imm); 155 default: 156 M5_UNREACHABLE; 157 } 158 } 159 case 0x5: 160 { 161 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 162 IntRegIndex rdzr = makeZero(rd); 163 uint32_t imm16 = bits(machInst, 20, 5); 164 uint32_t hw = bits(machInst, 22, 21); 165 switch (opc) { 166 case 0x0: 167 return new Movn(machInst, rdzr, imm16, hw * 16); 168 case 0x1: 169 return new Unknown64(machInst); 170 case 0x2: 171 return new Movz(machInst, rdzr, imm16, hw * 16); 172 case 0x3: 173 return new Movk(machInst, rdzr, imm16, hw * 16); 174 default: 175 M5_UNREACHABLE; 176 } 177 } 178 case 0x6: 179 if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5)))) 180 return new Unknown64(machInst); 181 switch (opc) { 182 case 0x0: 183 return new Sbfm64(machInst, rdzr, rn, immr, imms); 184 case 0x1: 185 return new Bfm64(machInst, rdzr, rn, immr, imms); 186 case 0x2: 187 return new Ubfm64(machInst, rdzr, rn, immr, imms); 188 case 0x3: 189 return new Unknown64(machInst); 190 default: 191 M5_UNREACHABLE; 192 } 193 case 0x7: 194 { 195 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 196 if (opc || bits(machInst, 21)) 197 return new Unknown64(machInst); 198 else 199 return new Extr64(machInst, rdzr, rn, rm, imms); 200 } 201 } 202 return new FailUnimplemented("Unhandled Case8", machInst); 203 } 204} 205}}; 206 207output decoder {{ 208namespace Aarch64 209{ 210 StaticInstPtr 211 decodeBranchExcSys(ExtMachInst machInst) 212 { 213 switch (bits(machInst, 30, 29)) { 214 case 0x0: 215 { 216 int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2; 217 if (bits(machInst, 31) == 0) 218 return new B64(machInst, imm); 219 else 220 return new Bl64(machInst, imm); 221 } 222 case 0x1: 223 { 224 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 225 if (bits(machInst, 25) == 0) { 226 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 227 if (bits(machInst, 24) == 0) 228 return new Cbz64(machInst, imm, rt); 229 else 230 return new Cbnz64(machInst, imm, rt); 231 } else { 232 uint64_t bitmask = 0x1; 233 bitmask <<= bits(machInst, 23, 19); 234 int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2; 235 if (bits(machInst, 31)) 236 bitmask <<= 32; 237 if (bits(machInst, 24) == 0) 238 return new Tbz64(machInst, bitmask, imm, rt); 239 else 240 return new Tbnz64(machInst, bitmask, imm, rt); 241 } 242 } 243 case 0x2: 244 // bit 30:26=10101 245 if (bits(machInst, 31) == 0) { 246 if (bits(machInst, 25, 24) || bits(machInst, 4)) 247 return new Unknown64(machInst); 248 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 249 ConditionCode condCode = 250 (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); 251 return new BCond64(machInst, imm, condCode); 252 } else if (bits(machInst, 25, 24) == 0x0) { 253 254 if (bits(machInst, 4, 2)) 255 return new Unknown64(machInst); 256 257 auto imm16 = bits(machInst, 20, 5); 258 uint8_t decVal = (bits(machInst, 1, 0) << 0) | 259 (bits(machInst, 23, 21) << 2); 260 261 switch (decVal) { 262 case 0x01: 263 return new Svc64(machInst, imm16); 264 case 0x02: 265 return new Hvc64(machInst, imm16); 266 case 0x03: 267 return new Smc64(machInst, imm16); 268 case 0x04: 269 return new Brk64(machInst, imm16); 270 case 0x08: 271 return new Hlt64(machInst, imm16); 272 case 0x15: 273 return new FailUnimplemented("dcps1", machInst); 274 case 0x16: 275 return new FailUnimplemented("dcps2", machInst); 276 case 0x17: 277 return new FailUnimplemented("dcps3", machInst); 278 default: 279 return new Unknown64(machInst); 280 } 281 } else if (bits(machInst, 25, 22) == 0x4) { 282 // bit 31:22=1101010100 283 bool l = bits(machInst, 21); 284 uint8_t op0 = bits(machInst, 20, 19); 285 uint8_t op1 = bits(machInst, 18, 16); 286 uint8_t crn = bits(machInst, 15, 12); 287 uint8_t crm = bits(machInst, 11, 8); 288 uint8_t op2 = bits(machInst, 7, 5); 289 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 290 switch (op0) { 291 case 0x0: 292 if (rt != 0x1f || l) 293 return new Unknown64(machInst); 294 if (crn == 0x2 && op1 == 0x3) { 295 switch (op2) { 296 case 0x0: 297 return new NopInst(machInst); 298 case 0x1: 299 return new YieldInst(machInst); 300 case 0x2: 301 return new WfeInst(machInst); 302 case 0x3: 303 return new WfiInst(machInst); 304 case 0x4: 305 return new SevInst(machInst); 306 case 0x5: 307 return new SevlInst(machInst); 308 default: 309 return new Unknown64(machInst); 310 } 311 } else if (crn == 0x3 && op1 == 0x3) { 312 switch (op2) { 313 case 0x2: 314 return new Clrex64(machInst); 315 case 0x4: 316 return new Dsb64(machInst); 317 case 0x5: 318 return new Dmb64(machInst); 319 case 0x6: 320 return new Isb64(machInst); 321 default: 322 return new Unknown64(machInst); 323 } 324 } else if (crn == 0x4) { 325 // MSR immediate 326 switch (op1 << 3 | op2) { 327 case 0x5: 328 // SP 329 return new MsrSP64(machInst, 330 (IntRegIndex) MISCREG_SPSEL, 331 INTREG_ZERO, 332 crm & 0x1); 333 case 0x1e: 334 // DAIFSet 335 return new MsrDAIFSet64( 336 machInst, 337 (IntRegIndex) MISCREG_DAIF, 338 INTREG_ZERO, 339 crm); 340 case 0x1f: 341 // DAIFClr 342 return new MsrDAIFClr64( 343 machInst, 344 (IntRegIndex) MISCREG_DAIF, 345 INTREG_ZERO, 346 crm); 347 default: 348 return new Unknown64(machInst); 349 } 350 } else { 351 return new Unknown64(machInst); 352 } 353 break; 354 case 0x1: 355 case 0x2: 356 case 0x3: 357 { 358 // bit 31:22=1101010100, 20:19=11 359 bool read = l; 360 MiscRegIndex miscReg = 361 decodeAArch64SysReg(op0, op1, crn, crm, op2); 362 if (read) { 363 if ((miscReg == MISCREG_DC_CIVAC_Xt) || 364 (miscReg == MISCREG_DC_CVAC_Xt) || 365 (miscReg == MISCREG_DC_IVAC_Xt) || 366 (miscReg == MISCREG_DC_ZVA_Xt)) { 367 return new Unknown64(machInst); 368 } 369 } 370 // Check for invalid registers 371 if (miscReg == MISCREG_UNKNOWN) { 372 auto full_mnemonic = 373 csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 374 read ? "mrs" : "msr", 375 op0, op1, crn, crm, op2); 376 377 return new FailUnimplemented(read ? "mrs" : "msr", 378 machInst, full_mnemonic); 379 380 } else if (miscReg == MISCREG_IMPDEF_UNIMPL) { 381 auto full_mnemonic = 382 csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 383 read ? "mrs" : "msr", 384 op0, op1, crn, crm, op2); 385 386 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 387 return new WarnUnimplemented(read ? "mrs" : "msr", 388 machInst, full_mnemonic + " treated as NOP"); 389 } else { 390 return new FailUnimplemented(read ? "mrs" : "msr", 391 machInst, full_mnemonic); 392 } 393 394 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 395 if (miscReg == MISCREG_NZCV) { 396 if (read) 397 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 398 else 399 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 400 } 401 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 402 if (read) { 403 StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); 404 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 405 si->setFlag(StaticInst::IsUnverifiable); 406 return si; 407 } else { 408 switch (miscReg) { 409 case MISCREG_DC_ZVA_Xt: 410 return new Dczva(machInst, rt, miscReg, iss); 411 case MISCREG_DC_CVAU_Xt: 412 return new Dccvau(machInst, rt, miscReg, iss); 413 case MISCREG_DC_CVAC_Xt: 414 return new Dccvac(machInst, rt, miscReg, iss); 415 case MISCREG_DC_CIVAC_Xt: 416 return new Dccivac(machInst, rt, miscReg, iss); 417 case MISCREG_DC_IVAC_Xt: 418 return new Dcivac(machInst, rt, miscReg, iss); 419 default: 420 return new Msr64(machInst, miscReg, rt, iss); 421 } 422 } 423 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 424 std::string full_mnem = csprintf("%s %s", 425 read ? "mrs" : "msr", miscRegName[miscReg]); 426 return new WarnUnimplemented(read ? "mrs" : "msr", 427 machInst, full_mnem); 428 } else { 429 return new FailUnimplemented(read ? "mrs" : "msr", 430 machInst, 431 csprintf("%s %s", 432 read ? "mrs" : "msr", 433 miscRegName[miscReg])); 434 } 435 } 436 break; 437 default: 438 M5_UNREACHABLE; 439 } 440 } else if (bits(machInst, 25) == 0x1) { 441 uint8_t opc = bits(machInst, 24, 21); 442 uint8_t op2 = bits(machInst, 20, 16); 443 uint8_t op3 = bits(machInst, 15, 10); 444 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 445 uint8_t op4 = bits(machInst, 4, 0); 446 if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0) 447 return new Unknown64(machInst); 448 switch (opc) { 449 case 0x0: 450 return new Br64(machInst, rn); 451 case 0x1: 452 return new Blr64(machInst, rn); 453 case 0x2: 454 return new Ret64(machInst, rn); 455 case 0x4: 456 if (rn != 0x1f) 457 return new Unknown64(machInst); 458 return new Eret64(machInst); 459 case 0x5: 460 if (rn != 0x1f) 461 return new Unknown64(machInst); 462 return new FailUnimplemented("dret", machInst); 463 default: 464 return new Unknown64(machInst); 465 } 466 } 467 M5_FALLTHROUGH; 468 default: 469 return new Unknown64(machInst); 470 } 471 return new FailUnimplemented("Unhandled Case7", machInst); 472 } 473} 474}}; 475 476output decoder {{ 477namespace Aarch64 478{ 479 StaticInstPtr 480 decodeLoadsStores(ExtMachInst machInst) 481 { 482 // bit 27,25=10 483 switch (bits(machInst, 29, 28)) { 484 case 0x0: 485 if (bits(machInst, 26) == 0) { 486 if (bits(machInst, 24) != 0) 487 return new Unknown64(machInst); 488 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 489 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 490 IntRegIndex rnsp = makeSP(rn); 491 IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 492 IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 493 uint8_t opc = (bits(machInst, 15) << 0) | 494 (bits(machInst, 23, 21) << 1); 495 uint8_t size = bits(machInst, 31, 30); 496 switch (opc) { 497 case 0x0: 498 switch (size) { 499 case 0x0: 500 return new STXRB64(machInst, rt, rnsp, rs); 501 case 0x1: 502 return new STXRH64(machInst, rt, rnsp, rs); 503 case 0x2: 504 return new STXRW64(machInst, rt, rnsp, rs); 505 case 0x3: 506 return new STXRX64(machInst, rt, rnsp, rs); 507 default: 508 M5_UNREACHABLE; 509 } 510 case 0x1: 511 switch (size) { 512 case 0x0: 513 return new STLXRB64(machInst, rt, rnsp, rs); 514 case 0x1: 515 return new STLXRH64(machInst, rt, rnsp, rs); 516 case 0x2: 517 return new STLXRW64(machInst, rt, rnsp, rs); 518 case 0x3: 519 return new STLXRX64(machInst, rt, rnsp, rs); 520 default: 521 M5_UNREACHABLE; 522 } 523 case 0x2: 524 switch (size) { 525 case 0x0: 526 case 0x1: 527 return new Unknown64(machInst); 528 case 0x2: 529 return new STXPW64(machInst, rs, rt, rt2, rnsp); 530 case 0x3: 531 return new STXPX64(machInst, rs, rt, rt2, rnsp); 532 default: 533 M5_UNREACHABLE; 534 } 535 536 case 0x3: 537 switch (size) { 538 case 0x0: 539 case 0x1: 540 return new Unknown64(machInst); 541 case 0x2: 542 return new STLXPW64(machInst, rs, rt, rt2, rnsp); 543 case 0x3: 544 return new STLXPX64(machInst, rs, rt, rt2, rnsp); 545 default: 546 M5_UNREACHABLE; 547 } 548 549 case 0x4: 550 switch (size) { 551 case 0x0: 552 return new LDXRB64(machInst, rt, rnsp, rs); 553 case 0x1: 554 return new LDXRH64(machInst, rt, rnsp, rs); 555 case 0x2: 556 return new LDXRW64(machInst, rt, rnsp, rs); 557 case 0x3: 558 return new LDXRX64(machInst, rt, rnsp, rs); 559 default: 560 M5_UNREACHABLE; 561 } 562 case 0x5: 563 switch (size) { 564 case 0x0: 565 return new LDAXRB64(machInst, rt, rnsp, rs); 566 case 0x1: 567 return new LDAXRH64(machInst, rt, rnsp, rs); 568 case 0x2: 569 return new LDAXRW64(machInst, rt, rnsp, rs); 570 case 0x3: 571 return new LDAXRX64(machInst, rt, rnsp, rs); 572 default: 573 M5_UNREACHABLE; 574 } 575 case 0x6: 576 switch (size) { 577 case 0x0: 578 case 0x1: 579 return new Unknown64(machInst); 580 case 0x2: 581 return new LDXPW64(machInst, rt, rt2, rnsp); 582 case 0x3: 583 return new LDXPX64(machInst, rt, rt2, rnsp); 584 default: 585 M5_UNREACHABLE; 586 } 587 588 case 0x7: 589 switch (size) { 590 case 0x0: 591 case 0x1: 592 return new Unknown64(machInst); 593 case 0x2: 594 return new LDAXPW64(machInst, rt, rt2, rnsp); 595 case 0x3: 596 return new LDAXPX64(machInst, rt, rt2, rnsp); 597 default: 598 M5_UNREACHABLE; 599 } 600 601 case 0x9: 602 switch (size) { 603 case 0x0: 604 return new STLRB64(machInst, rt, rnsp); 605 case 0x1: 606 return new STLRH64(machInst, rt, rnsp); 607 case 0x2: 608 return new STLRW64(machInst, rt, rnsp); 609 case 0x3: 610 return new STLRX64(machInst, rt, rnsp); 611 default: 612 M5_UNREACHABLE; 613 } 614 case 0xd: 615 switch (size) { 616 case 0x0: 617 return new LDARB64(machInst, rt, rnsp); 618 case 0x1: 619 return new LDARH64(machInst, rt, rnsp); 620 case 0x2: 621 return new LDARW64(machInst, rt, rnsp); 622 case 0x3: 623 return new LDARX64(machInst, rt, rnsp); 624 default: 625 M5_UNREACHABLE; 626 } 627 default: 628 return new Unknown64(machInst); 629 } 630 } else if (bits(machInst, 31)) { 631 return new Unknown64(machInst); 632 } else { 633 return decodeNeonMem(machInst); 634 } 635 case 0x1: 636 { 637 if (bits(machInst, 24) != 0) 638 return new Unknown64(machInst); 639 uint8_t switchVal = (bits(machInst, 26) << 0) | 640 (bits(machInst, 31, 30) << 1); 641 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 642 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 643 switch (switchVal) { 644 case 0x0: 645 return new LDRWL64_LIT(machInst, rt, imm); 646 case 0x1: 647 return new LDRSFP64_LIT(machInst, rt, imm); 648 case 0x2: 649 return new LDRXL64_LIT(machInst, rt, imm); 650 case 0x3: 651 return new LDRDFP64_LIT(machInst, rt, imm); 652 case 0x4: 653 return new LDRSWL64_LIT(machInst, rt, imm); 654 case 0x5: 655 return new BigFpMemLit("ldr", machInst, rt, imm); 656 case 0x6: 657 return new PRFM64_LIT(machInst, rt, imm); 658 default: 659 return new Unknown64(machInst); 660 } 661 } 662 case 0x2: 663 { 664 uint8_t opc = bits(machInst, 31, 30); 665 if (opc >= 3) 666 return new Unknown64(machInst); 667 uint32_t size = 0; 668 bool fp = bits(machInst, 26); 669 bool load = bits(machInst, 22); 670 if (fp) { 671 size = 4 << opc; 672 } else { 673 if ((opc == 1) && !load) 674 return new Unknown64(machInst); 675 size = (opc == 0 || opc == 1) ? 4 : 8; 676 } 677 uint8_t type = bits(machInst, 24, 23); 678 int64_t imm = sext<7>(bits(machInst, 21, 15)) * size; 679 680 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 681 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 682 IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 683 684 bool noAlloc = (type == 0); 685 bool signExt = !noAlloc && !fp && opc == 1; 686 PairMemOp::AddrMode mode; 687 const char *mnemonic = NULL; 688 switch (type) { 689 case 0x0: 690 case 0x2: 691 mode = PairMemOp::AddrMd_Offset; 692 break; 693 case 0x1: 694 mode = PairMemOp::AddrMd_PostIndex; 695 break; 696 case 0x3: 697 mode = PairMemOp::AddrMd_PreIndex; 698 break; 699 default: 700 return new Unknown64(machInst); 701 } 702 if (load) { 703 if (noAlloc) 704 mnemonic = "ldnp"; 705 else if (signExt) 706 mnemonic = "ldpsw"; 707 else 708 mnemonic = "ldp"; 709 } else { 710 if (noAlloc) 711 mnemonic = "stnp"; 712 else 713 mnemonic = "stp"; 714 } 715 716 return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc, 717 signExt, false, false, imm, mode, rn, rt, rt2); 718 } 719 // bit 29:27=111, 25=0 720 case 0x3: 721 { 722 uint8_t switchVal = (bits(machInst, 23, 22) << 0) | 723 (bits(machInst, 26) << 2) | 724 (bits(machInst, 31, 30) << 3); 725 if (bits(machInst, 24) == 1) { 726 uint64_t imm12 = bits(machInst, 21, 10); 727 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 728 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 729 IntRegIndex rnsp = makeSP(rn); 730 switch (switchVal) { 731 case 0x00: 732 return new STRB64_IMM(machInst, rt, rnsp, imm12); 733 case 0x01: 734 return new LDRB64_IMM(machInst, rt, rnsp, imm12); 735 case 0x02: 736 return new LDRSBX64_IMM(machInst, rt, rnsp, imm12); 737 case 0x03: 738 return new LDRSBW64_IMM(machInst, rt, rnsp, imm12); 739 case 0x04: 740 return new STRBFP64_IMM(machInst, rt, rnsp, imm12); 741 case 0x05: 742 return new LDRBFP64_IMM(machInst, rt, rnsp, imm12); 743 case 0x06: 744 return new BigFpMemImm("str", machInst, false, 745 rt, rnsp, imm12 << 4); 746 case 0x07: 747 return new BigFpMemImm("ldr", machInst, true, 748 rt, rnsp, imm12 << 4); 749 case 0x08: 750 return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1); 751 case 0x09: 752 return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1); 753 case 0x0a: 754 return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1); 755 case 0x0b: 756 return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1); 757 case 0x0c: 758 return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 759 case 0x0d: 760 return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 761 case 0x10: 762 return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2); 763 case 0x11: 764 return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2); 765 case 0x12: 766 return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2); 767 case 0x14: 768 return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 769 case 0x15: 770 return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 771 case 0x18: 772 return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3); 773 case 0x19: 774 return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3); 775 case 0x1a: 776 return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3); 777 case 0x1c: 778 return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 779 case 0x1d: 780 return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 781 default: 782 return new Unknown64(machInst); 783 } 784 } else if (bits(machInst, 21) == 1) { 785 if (bits(machInst, 11, 10) != 0x2) 786 return new Unknown64(machInst); 787 if (!bits(machInst, 14)) 788 return new Unknown64(machInst); 789 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 790 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 791 IntRegIndex rnsp = makeSP(rn); 792 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 793 ArmExtendType type = 794 (ArmExtendType)(uint32_t)bits(machInst, 15, 13); 795 uint8_t s = bits(machInst, 12); 796 switch (switchVal) { 797 case 0x00: 798 return new STRB64_REG(machInst, rt, rnsp, rm, type, 0); 799 case 0x01: 800 return new LDRB64_REG(machInst, rt, rnsp, rm, type, 0); 801 case 0x02: 802 return new LDRSBX64_REG(machInst, rt, rnsp, rm, type, 0); 803 case 0x03: 804 return new LDRSBW64_REG(machInst, rt, rnsp, rm, type, 0); 805 case 0x04: 806 return new STRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 807 case 0x05: 808 return new LDRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 809 case 0x6: 810 return new BigFpMemReg("str", machInst, false, 811 rt, rnsp, rm, type, s * 4); 812 case 0x7: 813 return new BigFpMemReg("ldr", machInst, true, 814 rt, rnsp, rm, type, s * 4); 815 case 0x08: 816 return new STRH64_REG(machInst, rt, rnsp, rm, type, s); 817 case 0x09: 818 return new LDRH64_REG(machInst, rt, rnsp, rm, type, s); 819 case 0x0a: 820 return new LDRSHX64_REG(machInst, rt, rnsp, rm, type, s); 821 case 0x0b: 822 return new LDRSHW64_REG(machInst, rt, rnsp, rm, type, s); 823 case 0x0c: 824 return new STRHFP64_REG(machInst, rt, rnsp, rm, type, s); 825 case 0x0d: 826 return new LDRHFP64_REG(machInst, rt, rnsp, rm, type, s); 827 case 0x10: 828 return new STRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 829 case 0x11: 830 return new LDRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 831 case 0x12: 832 return new LDRSW64_REG(machInst, rt, rnsp, rm, type, s * 2); 833 case 0x14: 834 return new STRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 835 case 0x15: 836 return new LDRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 837 case 0x18: 838 return new STRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 839 case 0x19: 840 return new LDRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 841 case 0x1a: 842 return new PRFM64_REG(machInst, rt, rnsp, rm, type, s * 3); 843 case 0x1c: 844 return new STRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 845 case 0x1d: 846 return new LDRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 847 default: 848 return new Unknown64(machInst); 849 } 850 } else { 851 // bit 29:27=111, 25:24=00, 21=0 852 switch (bits(machInst, 11, 10)) { 853 case 0x0: 854 { 855 IntRegIndex rt = 856 (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 857 IntRegIndex rn = 858 (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 859 IntRegIndex rnsp = makeSP(rn); 860 uint64_t imm = sext<9>(bits(machInst, 20, 12)); 861 switch (switchVal) { 862 case 0x00: 863 return new STURB64_IMM(machInst, rt, rnsp, imm); 864 case 0x01: 865 return new LDURB64_IMM(machInst, rt, rnsp, imm); 866 case 0x02: 867 return new LDURSBX64_IMM(machInst, rt, rnsp, imm); 868 case 0x03: 869 return new LDURSBW64_IMM(machInst, rt, rnsp, imm); 870 case 0x04: 871 return new STURBFP64_IMM(machInst, rt, rnsp, imm); 872 case 0x05: 873 return new LDURBFP64_IMM(machInst, rt, rnsp, imm); 874 case 0x06: 875 return new BigFpMemImm("stur", machInst, false, 876 rt, rnsp, imm); 877 case 0x07: 878 return new BigFpMemImm("ldur", machInst, true, 879 rt, rnsp, imm); 880 case 0x08: 881 return new STURH64_IMM(machInst, rt, rnsp, imm); 882 case 0x09: 883 return new LDURH64_IMM(machInst, rt, rnsp, imm); 884 case 0x0a: 885 return new LDURSHX64_IMM(machInst, rt, rnsp, imm); 886 case 0x0b: 887 return new LDURSHW64_IMM(machInst, rt, rnsp, imm); 888 case 0x0c: 889 return new STURHFP64_IMM(machInst, rt, rnsp, imm); 890 case 0x0d: 891 return new LDURHFP64_IMM(machInst, rt, rnsp, imm); 892 case 0x10: 893 return new STURW64_IMM(machInst, rt, rnsp, imm); 894 case 0x11: 895 return new LDURW64_IMM(machInst, rt, rnsp, imm); 896 case 0x12: 897 return new LDURSW64_IMM(machInst, rt, rnsp, imm); 898 case 0x14: 899 return new STURSFP64_IMM(machInst, rt, rnsp, imm); 900 case 0x15: 901 return new LDURSFP64_IMM(machInst, rt, rnsp, imm); 902 case 0x18: 903 return new STURX64_IMM(machInst, rt, rnsp, imm); 904 case 0x19: 905 return new LDURX64_IMM(machInst, rt, rnsp, imm); 906 case 0x1a: 907 return new PRFUM64_IMM(machInst, rt, rnsp, imm); 908 case 0x1c: 909 return new STURDFP64_IMM(machInst, rt, rnsp, imm); 910 case 0x1d: 911 return new LDURDFP64_IMM(machInst, rt, rnsp, imm); 912 default: 913 return new Unknown64(machInst); 914 } 915 } 916 // bit 29:27=111, 25:24=00, 21=0, 11:10=01 917 case 0x1: 918 { 919 IntRegIndex rt = 920 (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 921 IntRegIndex rn = 922 (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 923 IntRegIndex rnsp = makeSP(rn); 924 uint64_t imm = sext<9>(bits(machInst, 20, 12)); 925 switch (switchVal) { 926 case 0x00: 927 return new STRB64_POST(machInst, rt, rnsp, imm); 928 case 0x01: 929 return new LDRB64_POST(machInst, rt, rnsp, imm); 930 case 0x02: 931 return new LDRSBX64_POST(machInst, rt, rnsp, imm); 932 case 0x03: 933 return new LDRSBW64_POST(machInst, rt, rnsp, imm); 934 case 0x04: 935 return new STRBFP64_POST(machInst, rt, rnsp, imm); 936 case 0x05: 937 return new LDRBFP64_POST(machInst, rt, rnsp, imm); 938 case 0x06: 939 return new BigFpMemPost("str", machInst, false, 940 rt, rnsp, imm); 941 case 0x07: 942 return new BigFpMemPost("ldr", machInst, true, 943 rt, rnsp, imm); 944 case 0x08: 945 return new STRH64_POST(machInst, rt, rnsp, imm); 946 case 0x09: 947 return new LDRH64_POST(machInst, rt, rnsp, imm); 948 case 0x0a: 949 return new LDRSHX64_POST(machInst, rt, rnsp, imm); 950 case 0x0b: 951 return new LDRSHW64_POST(machInst, rt, rnsp, imm); 952 case 0x0c: 953 return new STRHFP64_POST(machInst, rt, rnsp, imm); 954 case 0x0d: 955 return new LDRHFP64_POST(machInst, rt, rnsp, imm); 956 case 0x10: 957 return new STRW64_POST(machInst, rt, rnsp, imm); 958 case 0x11: 959 return new LDRW64_POST(machInst, rt, rnsp, imm); 960 case 0x12: 961 return new LDRSW64_POST(machInst, rt, rnsp, imm); 962 case 0x14: 963 return new STRSFP64_POST(machInst, rt, rnsp, imm); 964 case 0x15: 965 return new LDRSFP64_POST(machInst, rt, rnsp, imm); 966 case 0x18: 967 return new STRX64_POST(machInst, rt, rnsp, imm); 968 case 0x19: 969 return new LDRX64_POST(machInst, rt, rnsp, imm); 970 case 0x1c: 971 return new STRDFP64_POST(machInst, rt, rnsp, imm); 972 case 0x1d: 973 return new LDRDFP64_POST(machInst, rt, rnsp, imm); 974 default: 975 return new Unknown64(machInst); 976 } 977 } 978 case 0x2: 979 { 980 IntRegIndex rt = 981 (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 982 IntRegIndex rn = 983 (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 984 IntRegIndex rnsp = makeSP(rn); 985 uint64_t imm = sext<9>(bits(machInst, 20, 12)); 986 switch (switchVal) { 987 case 0x00: 988 return new STTRB64_IMM(machInst, rt, rnsp, imm); 989 case 0x01: 990 return new LDTRB64_IMM(machInst, rt, rnsp, imm); 991 case 0x02: 992 return new LDTRSBX64_IMM(machInst, rt, rnsp, imm); 993 case 0x03: 994 return new LDTRSBW64_IMM(machInst, rt, rnsp, imm); 995 case 0x08: 996 return new STTRH64_IMM(machInst, rt, rnsp, imm); 997 case 0x09: 998 return new LDTRH64_IMM(machInst, rt, rnsp, imm); 999 case 0x0a: 1000 return new LDTRSHX64_IMM(machInst, rt, rnsp, imm); 1001 case 0x0b: 1002 return new LDTRSHW64_IMM(machInst, rt, rnsp, imm); 1003 case 0x10: 1004 return new STTRW64_IMM(machInst, rt, rnsp, imm); 1005 case 0x11: 1006 return new LDTRW64_IMM(machInst, rt, rnsp, imm); 1007 case 0x12: 1008 return new LDTRSW64_IMM(machInst, rt, rnsp, imm); 1009 case 0x18: 1010 return new STTRX64_IMM(machInst, rt, rnsp, imm); 1011 case 0x19: 1012 return new LDTRX64_IMM(machInst, rt, rnsp, imm); 1013 default: 1014 return new Unknown64(machInst); 1015 } 1016 } 1017 case 0x3: 1018 { 1019 IntRegIndex rt = 1020 (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 1021 IntRegIndex rn = 1022 (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 1023 IntRegIndex rnsp = makeSP(rn); 1024 uint64_t imm = sext<9>(bits(machInst, 20, 12)); 1025 switch (switchVal) { 1026 case 0x00: 1027 return new STRB64_PRE(machInst, rt, rnsp, imm); 1028 case 0x01: 1029 return new LDRB64_PRE(machInst, rt, rnsp, imm); 1030 case 0x02: 1031 return new LDRSBX64_PRE(machInst, rt, rnsp, imm); 1032 case 0x03: 1033 return new LDRSBW64_PRE(machInst, rt, rnsp, imm); 1034 case 0x04: 1035 return new STRBFP64_PRE(machInst, rt, rnsp, imm); 1036 case 0x05: 1037 return new LDRBFP64_PRE(machInst, rt, rnsp, imm); 1038 case 0x06: 1039 return new BigFpMemPre("str", machInst, false, 1040 rt, rnsp, imm); 1041 case 0x07: 1042 return new BigFpMemPre("ldr", machInst, true, 1043 rt, rnsp, imm); 1044 case 0x08: 1045 return new STRH64_PRE(machInst, rt, rnsp, imm); 1046 case 0x09: 1047 return new LDRH64_PRE(machInst, rt, rnsp, imm); 1048 case 0x0a: 1049 return new LDRSHX64_PRE(machInst, rt, rnsp, imm); 1050 case 0x0b: 1051 return new LDRSHW64_PRE(machInst, rt, rnsp, imm); 1052 case 0x0c: 1053 return new STRHFP64_PRE(machInst, rt, rnsp, imm); 1054 case 0x0d: 1055 return new LDRHFP64_PRE(machInst, rt, rnsp, imm); 1056 case 0x10: 1057 return new STRW64_PRE(machInst, rt, rnsp, imm); 1058 case 0x11: 1059 return new LDRW64_PRE(machInst, rt, rnsp, imm); 1060 case 0x12: 1061 return new LDRSW64_PRE(machInst, rt, rnsp, imm); 1062 case 0x14: 1063 return new STRSFP64_PRE(machInst, rt, rnsp, imm); 1064 case 0x15: 1065 return new LDRSFP64_PRE(machInst, rt, rnsp, imm); 1066 case 0x18: 1067 return new STRX64_PRE(machInst, rt, rnsp, imm); 1068 case 0x19: 1069 return new LDRX64_PRE(machInst, rt, rnsp, imm); 1070 case 0x1c: 1071 return new STRDFP64_PRE(machInst, rt, rnsp, imm); 1072 case 0x1d: 1073 return new LDRDFP64_PRE(machInst, rt, rnsp, imm); 1074 default: 1075 return new Unknown64(machInst); 1076 } 1077 } 1078 default: 1079 M5_UNREACHABLE; 1080 } 1081 } 1082 } 1083 default: 1084 M5_UNREACHABLE; 1085 } 1086 return new FailUnimplemented("Unhandled Case1", machInst); 1087 } 1088} 1089}}; 1090 1091output decoder {{ 1092namespace Aarch64 1093{ 1094 StaticInstPtr 1095 decodeDataProcReg(ExtMachInst machInst) 1096 { 1097 uint8_t switchVal = (bits(machInst, 28) << 1) | 1098 (bits(machInst, 24) << 0); 1099 switch (switchVal) { 1100 case 0x0: 1101 { 1102 uint8_t switchVal = (bits(machInst, 21) << 0) | 1103 (bits(machInst, 30, 29) << 1); 1104 ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 1105 uint8_t imm6 = bits(machInst, 15, 10); 1106 bool sf = bits(machInst, 31); 1107 if (!sf && (imm6 & 0x20)) 1108 return new Unknown64(machInst); 1109 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 1110 IntRegIndex rdzr = makeZero(rd); 1111 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 1112 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 1113 1114 switch (switchVal) { 1115 case 0x0: 1116 return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); 1117 case 0x1: 1118 return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); 1119 case 0x2: 1120 return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); 1121 case 0x3: 1122 return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); 1123 case 0x4: 1124 return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); 1125 case 0x5: 1126 return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); 1127 case 0x6: 1128 return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); 1129 case 0x7: 1130 return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); 1131 default: 1132 M5_UNREACHABLE; 1133 } 1134 } 1135 case 0x1: 1136 { 1137 uint8_t switchVal = bits(machInst, 30, 29); 1138 if (bits(machInst, 21) == 0) { 1139 ArmShiftType type = 1140 (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 1141 if (type == ROR) 1142 return new Unknown64(machInst); 1143 uint8_t imm6 = bits(machInst, 15, 10); 1144 if (!bits(machInst, 31) && bits(imm6, 5)) 1145 return new Unknown64(machInst); 1146 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 1147 IntRegIndex rdzr = makeZero(rd); 1148 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 1149 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 1150 switch (switchVal) { 1151 case 0x0: 1152 return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); 1153 case 0x1: 1154 return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); 1155 case 0x2: 1156 return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); 1157 case 0x3: 1158 return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); 1159 default: 1160 M5_UNREACHABLE; 1161 } 1162 } else { 1163 if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) 1164 return new Unknown64(machInst); 1165 ArmExtendType type = 1166 (ArmExtendType)(uint8_t)bits(machInst, 15, 13); 1167 uint8_t imm3 = bits(machInst, 12, 10); 1168 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 1169 IntRegIndex rdsp = makeSP(rd); 1170 IntRegIndex rdzr = makeZero(rd); 1171 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 1172 IntRegIndex rnsp = makeSP(rn); 1173 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 1174 1175 switch (switchVal) { 1176 case 0x0: 1177 return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); 1178 case 0x1: 1179 return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 1180 case 0x2: 1181 return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); 1182 case 0x3: 1183 return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 1184 default: 1185 M5_UNREACHABLE; 1186 } 1187 } 1188 } 1189 case 0x2: 1190 { 1191 if (bits(machInst, 21) == 1) 1192 return new Unknown64(machInst); 1193 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 1194 IntRegIndex rdzr = makeZero(rd); 1195 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 1196 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 1197 switch (bits(machInst, 23, 22)) { 1198 case 0x0: 1199 { 1200 if (bits(machInst, 15, 10)) 1201 return new Unknown64(machInst); 1202 uint8_t switchVal = bits(machInst, 30, 29); 1203 switch (switchVal) { 1204 case 0x0: 1205 return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL); 1206 case 0x1: 1207 return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 1208 case 0x2: 1209 return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL); 1210 case 0x3: 1211 return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 1212 default: 1213 M5_UNREACHABLE; 1214 } 1215 } 1216 case 0x1: 1217 { 1218 if ((bits(machInst, 4) == 1) || 1219 (bits(machInst, 10) == 1) || 1220 (bits(machInst, 29) == 0)) { 1221 return new Unknown64(machInst); 1222 } 1223 ConditionCode cond = 1224 (ConditionCode)(uint8_t)bits(machInst, 15, 12); 1225 uint8_t flags = bits(machInst, 3, 0); 1226 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 1227 if (bits(machInst, 11) == 0) { 1228 IntRegIndex rm = 1229 (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 1230 if (bits(machInst, 30) == 0) { 1231 return new CcmnReg64(machInst, rn, rm, cond, flags); 1232 } else { 1233 return new CcmpReg64(machInst, rn, rm, cond, flags); 1234 } 1235 } else { 1236 uint8_t imm5 = bits(machInst, 20, 16); 1237 if (bits(machInst, 30) == 0) { 1238 return new CcmnImm64(machInst, rn, imm5, cond, flags); 1239 } else { 1240 return new CcmpImm64(machInst, rn, imm5, cond, flags); 1241 } 1242 } 1243 } 1244 case 0x2: 1245 { 1246 if (bits(machInst, 29) == 1 || 1247 bits(machInst, 11) == 1) { 1248 return new Unknown64(machInst); 1249 } 1250 uint8_t switchVal = (bits(machInst, 10) << 0) | 1251 (bits(machInst, 30) << 1); 1252 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 1253 IntRegIndex rdzr = makeZero(rd); 1254 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 1255 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 1256 ConditionCode cond = 1257 (ConditionCode)(uint8_t)bits(machInst, 15, 12); 1258 switch (switchVal) { 1259 case 0x0: 1260 return new Csel64(machInst, rdzr, rn, rm, cond); 1261 case 0x1: 1262 return new Csinc64(machInst, rdzr, rn, rm, cond); 1263 case 0x2: 1264 return new Csinv64(machInst, rdzr, rn, rm, cond); 1265 case 0x3: 1266 return new Csneg64(machInst, rdzr, rn, rm, cond); 1267 default: 1268 M5_UNREACHABLE; 1269 } 1270 } 1271 case 0x3: 1272 if (bits(machInst, 30) == 0) { 1273 if (bits(machInst, 29) != 0) 1274 return new Unknown64(machInst); 1275 uint8_t switchVal = bits(machInst, 15, 10); 1276 switch (switchVal) { 1277 case 0x2: 1278 return new Udiv64(machInst, rdzr, rn, rm); 1279 case 0x3: 1280 return new Sdiv64(machInst, rdzr, rn, rm); 1281 case 0x8: 1282 return new Lslv64(machInst, rdzr, rn, rm); 1283 case 0x9: 1284 return new Lsrv64(machInst, rdzr, rn, rm); 1285 case 0xa: 1286 return new Asrv64(machInst, rdzr, rn, rm); 1287 case 0xb: 1288 return new Rorv64(machInst, rdzr, rn, rm); 1289 case 0x10: 1290 return new Crc32b64(machInst, rdzr, rn, rm); 1291 case 0x11: 1292 return new Crc32h64(machInst, rdzr, rn, rm); 1293 case 0x12: 1294 return new Crc32w64(machInst, rdzr, rn, rm); 1295 case 0x13: 1296 return new Crc32x64(machInst, rdzr, rn, rm); 1297 case 0x14: 1298 return new Crc32cb64(machInst, rdzr, rn, rm); 1299 case 0x15: 1300 return new Crc32ch64(machInst, rdzr, rn, rm); 1301 case 0x16: 1302 return new Crc32cw64(machInst, rdzr, rn, rm); 1303 case 0x17: 1304 return new Crc32cx64(machInst, rdzr, rn, rm); 1305 default: 1306 return new Unknown64(machInst); 1307 } 1308 } else { 1309 if (bits(machInst, 20, 16) != 0 || 1310 bits(machInst, 29) != 0) { 1311 return new Unknown64(machInst); 1312 } 1313 uint8_t switchVal = bits(machInst, 15, 10); 1314 switch (switchVal) { 1315 case 0x0: 1316 return new Rbit64(machInst, rdzr, rn); 1317 case 0x1: 1318 return new Rev1664(machInst, rdzr, rn); 1319 case 0x2: 1320 if (bits(machInst, 31) == 0) 1321 return new Rev64(machInst, rdzr, rn); 1322 else 1323 return new Rev3264(machInst, rdzr, rn); 1324 case 0x3: 1325 if (bits(machInst, 31) != 1) 1326 return new Unknown64(machInst); 1327 return new Rev64(machInst, rdzr, rn); 1328 case 0x4: 1329 return new Clz64(machInst, rdzr, rn); 1330 case 0x5: 1331 return new Cls64(machInst, rdzr, rn); 1332 default: 1333 return new Unknown64(machInst); 1334 } 1335 } 1336 default: 1337 M5_UNREACHABLE; 1338 } 1339 } 1340 case 0x3: 1341 { 1342 if (bits(machInst, 30, 29) != 0x0 || 1343 (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0)) 1344 return new Unknown64(machInst); 1345 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 1346 IntRegIndex rdzr = makeZero(rd); 1347 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 1348 IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 1349 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 1350 switch (bits(machInst, 23, 21)) { 1351 case 0x0: 1352 if (bits(machInst, 15) == 0) 1353 return new Madd64(machInst, rdzr, ra, rn, rm); 1354 else 1355 return new Msub64(machInst, rdzr, ra, rn, rm); 1356 case 0x1: 1357 if (bits(machInst, 15) == 0) 1358 return new Smaddl64(machInst, rdzr, ra, rn, rm); 1359 else 1360 return new Smsubl64(machInst, rdzr, ra, rn, rm); 1361 case 0x2: 1362 if (bits(machInst, 15) != 0) 1363 return new Unknown64(machInst); 1364 return new Smulh64(machInst, rdzr, rn, rm); 1365 case 0x5: 1366 if (bits(machInst, 15) == 0) 1367 return new Umaddl64(machInst, rdzr, ra, rn, rm); 1368 else 1369 return new Umsubl64(machInst, rdzr, ra, rn, rm); 1370 case 0x6: 1371 if (bits(machInst, 15) != 0) 1372 return new Unknown64(machInst); 1373 return new Umulh64(machInst, rdzr, rn, rm); 1374 default: 1375 return new Unknown64(machInst); 1376 } 1377 } 1378 default: 1379 M5_UNREACHABLE; 1380 } 1381 return new FailUnimplemented("Unhandled Case2", machInst); 1382 } 1383} 1384}}; 1385 1386output decoder {{ 1387namespace Aarch64 1388{ 1389 template <typename DecoderFeatures> 1390 StaticInstPtr 1391 decodeAdvSIMD(ExtMachInst machInst) 1392 { 1393 if (bits(machInst, 24) == 1) { 1394 if (bits(machInst, 10) == 0) { 1395 return decodeNeonIndexedElem<DecoderFeatures>(machInst); 1396 } else if (bits(machInst, 23) == 1) { 1397 return new Unknown64(machInst); 1398 } else { 1399 if (bits(machInst, 22, 19)) { 1400 return decodeNeonShiftByImm(machInst); 1401 } else { 1402 return decodeNeonModImm(machInst); 1403 } 1404 } 1405 } else if (bits(machInst, 21) == 1) { 1406 if (bits(machInst, 10) == 1) { 1407 return decodeNeon3Same<DecoderFeatures>(machInst); 1408 } else if (bits(machInst, 11) == 0) { 1409 return decodeNeon3Diff(machInst); 1410 } else if (bits(machInst, 20, 17) == 0x0) { 1411 return decodeNeon2RegMisc(machInst); 1412 } else if (bits(machInst, 20, 17) == 0x8) { 1413 return decodeNeonAcrossLanes(machInst); 1414 } else { 1415 return new Unknown64(machInst); 1416 } 1417 } else if (bits(machInst, 24) || 1418 bits(machInst, 21) || 1419 bits(machInst, 15)) { 1420 return new Unknown64(machInst); 1421 } else if (bits(machInst, 10) == 1) { 1422 if (bits(machInst, 23, 22)) 1423 return new Unknown64(machInst); 1424 return decodeNeonCopy(machInst); 1425 } else if (bits(machInst, 29) == 1) { 1426 return decodeNeonExt(machInst); 1427 } else if (bits(machInst, 11) == 1) { 1428 return decodeNeonZipUzpTrn(machInst); 1429 } else if (bits(machInst, 23, 22) == 0x0) { 1430 return decodeNeonTblTbx(machInst); 1431 } else { 1432 return new Unknown64(machInst); 1433 } 1434 return new FailUnimplemented("Unhandled Case3", machInst); 1435 } 1436} 1437}}; 1438 1439 1440output decoder {{ 1441namespace Aarch64 1442{ 1443 StaticInstPtr 1444 // bit 30=0, 28:25=1111 1445 decodeFp(ExtMachInst machInst) 1446 { 1447 if (bits(machInst, 24) == 1) { 1448 if (bits(machInst, 31) || bits(machInst, 29)) 1449 return new Unknown64(machInst); 1450 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 1451 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 1452 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 1453 IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10); 1454 uint8_t switchVal = (bits(machInst, 23, 21) << 1) | 1455 (bits(machInst, 15) << 0); 1456 switch (switchVal) { 1457 case 0x0: // FMADD Sd = Sa + Sn*Sm 1458 return new FMAddS(machInst, rd, rn, rm, ra); 1459 case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm 1460 return new FMSubS(machInst, rd, rn, rm, ra); 1461 case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm 1462 return new FNMAddS(machInst, rd, rn, rm, ra); 1463 case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm 1464 return new FNMSubS(machInst, rd, rn, rm, ra); 1465 case 0x4: // FMADD Dd = Da + Dn*Dm 1466 return new FMAddD(machInst, rd, rn, rm, ra); 1467 case 0x5: // FMSUB Dd = Da + (-Dn)*Dm 1468 return new FMSubD(machInst, rd, rn, rm, ra); 1469 case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm 1470 return new FNMAddD(machInst, rd, rn, rm, ra); 1471 case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm 1472 return new FNMSubD(machInst, rd, rn, rm, ra); 1473 default: 1474 return new Unknown64(machInst); 1475 } 1476 } else if (bits(machInst, 21) == 0) { 1477 bool s = bits(machInst, 29); 1478 if (s) 1479 return new Unknown64(machInst); 1480 uint8_t switchVal = bits(machInst, 20, 16); 1481 uint8_t type = bits(machInst, 23, 22); 1482 uint8_t scale = bits(machInst, 15, 10); 1483 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 1484 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 1485 if (bits(machInst, 18, 17) == 3 && scale != 0) 1486 return new Unknown64(machInst); 1487 // 30:24=0011110, 21=0 1488 switch (switchVal) { 1489 case 0x00: 1490 return new FailUnimplemented("fcvtns", machInst); 1491 case 0x01: 1492 return new FailUnimplemented("fcvtnu", machInst); 1493 case 0x02: 1494 switch ( (bits(machInst, 31) << 2) | type ) { 1495 case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits)) 1496 return new FcvtSFixedFpSW(machInst, rd, rn, scale); 1497 case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits)) 1498 return new FcvtSFixedFpDW(machInst, rd, rn, scale); 1499 case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits)) 1500 return new FcvtSFixedFpSX(machInst, rd, rn, scale); 1501 case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits)) 1502 return new FcvtSFixedFpDX(machInst, rd, rn, scale); 1503 default: 1504 return new Unknown64(machInst); 1505 } 1506 case 0x03: 1507 switch ( (bits(machInst, 31) << 2) | type ) { 1508 case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits)) 1509 return new FcvtUFixedFpSW(machInst, rd, rn, scale); 1510 case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits)) 1511 return new FcvtUFixedFpDW(machInst, rd, rn, scale); 1512 case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits)) 1513 return new FcvtUFixedFpSX(machInst, rd, rn, scale); 1514 case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits)) 1515 return new FcvtUFixedFpDX(machInst, rd, rn, scale); 1516 default: 1517 return new Unknown64(machInst); 1518 } 1519 case 0x04: 1520 return new FailUnimplemented("fcvtas", machInst); 1521 case 0x05: 1522 return new FailUnimplemented("fcvtau", machInst); 1523 case 0x08: 1524 return new FailUnimplemented("fcvtps", machInst); 1525 case 0x09: 1526 return new FailUnimplemented("fcvtpu", machInst); 1527 case 0x0e: 1528 return new FailUnimplemented("fmov elem. to 64", machInst); 1529 case 0x0f: 1530 return new FailUnimplemented("fmov 64 bit", machInst); 1531 case 0x10: 1532 return new FailUnimplemented("fcvtms", machInst); 1533 case 0x11: 1534 return new FailUnimplemented("fcvtmu", machInst); 1535 case 0x18: 1536 switch ( (bits(machInst, 31) << 2) | type ) { 1537 case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 1538 return new FcvtFpSFixedSW(machInst, rd, rn, scale); 1539 case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 1540 return new FcvtFpSFixedDW(machInst, rd, rn, scale); 1541 case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 1542 return new FcvtFpSFixedSX(machInst, rd, rn, scale); 1543 case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 1544 return new FcvtFpSFixedDX(machInst, rd, rn, scale); 1545 default: 1546 return new Unknown64(machInst); 1547 } 1548 case 0x19: 1549 switch ( (bits(machInst, 31) << 2) | type ) { 1550 case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 1551 return new FcvtFpUFixedSW(machInst, rd, rn, scale); 1552 case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 1553 return new FcvtFpUFixedDW(machInst, rd, rn, scale); 1554 case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 1555 return new FcvtFpUFixedSX(machInst, rd, rn, scale); 1556 case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 1557 return new FcvtFpUFixedDX(machInst, rd, rn, scale); 1558 default: 1559 return new Unknown64(machInst); 1560 } 1561 default: 1562 return new Unknown64(machInst); 1563 } 1564 } else { 1565 // 30=0, 28:24=11110, 21=1 1566 uint8_t type = bits(machInst, 23, 22); 1567 uint8_t imm8 = bits(machInst, 20, 13); 1568 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 1569 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 1570 switch (bits(machInst, 11, 10)) { 1571 case 0x0: 1572 if (bits(machInst, 12) == 1) { 1573 if (bits(machInst, 31) || 1574 bits(machInst, 29) || 1575 bits(machInst, 9, 5)) { 1576 return new Unknown64(machInst); 1577 } 1578 // 31:29=000, 28:24=11110, 21=1, 12:10=100 1579 if (type == 0) { 1580 // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5) 1581 // :imm8<5:0>:Zeros(19) 1582 uint32_t imm = vfp_modified_imm(imm8, false); 1583 return new FmovImmS(machInst, rd, imm); 1584 } else if (type == 1) { 1585 // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8) 1586 // :imm8<5:0>:Zeros(48) 1587 uint64_t imm = vfp_modified_imm(imm8, true); 1588 return new FmovImmD(machInst, rd, imm); 1589 } else { 1590 return new Unknown64(machInst); 1591 } 1592 } else if (bits(machInst, 13) == 1) { 1593 if (bits(machInst, 31) || 1594 bits(machInst, 29) || 1595 bits(machInst, 15, 14) || 1596 bits(machInst, 23) || 1597 bits(machInst, 2, 0)) { 1598 return new Unknown64(machInst); 1599 } 1600 uint8_t switchVal = (bits(machInst, 4, 3) << 0) | 1601 (bits(machInst, 22) << 2); 1602 IntRegIndex rm = (IntRegIndex)(uint32_t) 1603 bits(machInst, 20, 16); 1604 // 28:23=000111100, 21=1, 15:10=001000, 2:0=000 1605 switch (switchVal) { 1606 case 0x0: 1607 // FCMP flags = compareQuiet(Sn,Sm) 1608 return new FCmpRegS(machInst, rn, rm); 1609 case 0x1: 1610 // FCMP flags = compareQuiet(Sn,0.0) 1611 return new FCmpImmS(machInst, rn, 0); 1612 case 0x2: 1613 // FCMPE flags = compareSignaling(Sn,Sm) 1614 return new FCmpERegS(machInst, rn, rm); 1615 case 0x3: 1616 // FCMPE flags = compareSignaling(Sn,0.0) 1617 return new FCmpEImmS(machInst, rn, 0); 1618 case 0x4: 1619 // FCMP flags = compareQuiet(Dn,Dm) 1620 return new FCmpRegD(machInst, rn, rm); 1621 case 0x5: 1622 // FCMP flags = compareQuiet(Dn,0.0) 1623 return new FCmpImmD(machInst, rn, 0); 1624 case 0x6: 1625 // FCMPE flags = compareSignaling(Dn,Dm) 1626 return new FCmpERegD(machInst, rn, rm); 1627 case 0x7: 1628 // FCMPE flags = compareSignaling(Dn,0.0) 1629 return new FCmpEImmD(machInst, rn, 0); 1630 default: 1631 return new Unknown64(machInst); 1632 } 1633 } else if (bits(machInst, 14) == 1) { 1634 if (bits(machInst, 31) || bits(machInst, 29)) 1635 return new Unknown64(machInst); 1636 uint8_t opcode = bits(machInst, 20, 15); 1637 // Bits 31:24=00011110, 21=1, 14:10=10000 1638 switch (opcode) { 1639 case 0x0: 1640 if (type == 0) 1641 // FMOV Sd = Sn 1642 return new FmovRegS(machInst, rd, rn); 1643 else if (type == 1) 1644 // FMOV Dd = Dn 1645 return new FmovRegD(machInst, rd, rn); 1646 break; 1647 case 0x1: 1648 if (type == 0) 1649 // FABS Sd = abs(Sn) 1650 return new FAbsS(machInst, rd, rn); 1651 else if (type == 1) 1652 // FABS Dd = abs(Dn) 1653 return new FAbsD(machInst, rd, rn); 1654 break; 1655 case 0x2: 1656 if (type == 0) 1657 // FNEG Sd = -Sn 1658 return new FNegS(machInst, rd, rn); 1659 else if (type == 1) 1660 // FNEG Dd = -Dn 1661 return new FNegD(machInst, rd, rn); 1662 break; 1663 case 0x3: 1664 if (type == 0) 1665 // FSQRT Sd = sqrt(Sn) 1666 return new FSqrtS(machInst, rd, rn); 1667 else if (type == 1) 1668 // FSQRT Dd = sqrt(Dn) 1669 return new FSqrtD(machInst, rd, rn); 1670 break; 1671 case 0x4: 1672 if (type == 1) 1673 // FCVT Sd = convertFormat(Dn) 1674 return new FcvtFpDFpS(machInst, rd, rn); 1675 else if (type == 3) 1676 // FCVT Sd = convertFormat(Hn) 1677 return new FcvtFpHFpS(machInst, rd, rn); 1678 break; 1679 case 0x5: 1680 if (type == 0) 1681 // FCVT Dd = convertFormat(Sn) 1682 return new FCvtFpSFpD(machInst, rd, rn); 1683 else if (type == 3) 1684 // FCVT Dd = convertFormat(Hn) 1685 return new FcvtFpHFpD(machInst, rd, rn); 1686 break; 1687 case 0x7: 1688 if (type == 0) 1689 // FCVT Hd = convertFormat(Sn) 1690 return new FcvtFpSFpH(machInst, rd, rn); 1691 else if (type == 1) 1692 // FCVT Hd = convertFormat(Dn) 1693 return new FcvtFpDFpH(machInst, rd, rn); 1694 break; 1695 case 0x8: 1696 if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn) 1697 return new FRIntNS(machInst, rd, rn); 1698 else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn) 1699 return new FRIntND(machInst, rd, rn); 1700 break; 1701 case 0x9: 1702 if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn) 1703 return new FRIntPS(machInst, rd, rn); 1704 else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn) 1705 return new FRIntPD(machInst, rd, rn); 1706 break; 1707 case 0xa: 1708 if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn) 1709 return new FRIntMS(machInst, rd, rn); 1710 else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn) 1711 return new FRIntMD(machInst, rd, rn); 1712 break; 1713 case 0xb: 1714 if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn) 1715 return new FRIntZS(machInst, rd, rn); 1716 else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn) 1717 return new FRIntZD(machInst, rd, rn); 1718 break; 1719 case 0xc: 1720 if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn) 1721 return new FRIntAS(machInst, rd, rn); 1722 else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn) 1723 return new FRIntAD(machInst, rd, rn); 1724 break; 1725 case 0xe: 1726 if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn) 1727 return new FRIntXS(machInst, rd, rn); 1728 else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn) 1729 return new FRIntXD(machInst, rd, rn); 1730 break; 1731 case 0xf: 1732 if (type == 0) // FRINTI Sd = roundToIntegral(Sn) 1733 return new FRIntIS(machInst, rd, rn); 1734 else if (type == 1) // FRINTI Dd = roundToIntegral(Dn) 1735 return new FRIntID(machInst, rd, rn); 1736 break; 1737 default: 1738 return new Unknown64(machInst); 1739 } 1740 return new Unknown64(machInst); 1741 } else if (bits(machInst, 15) == 1) { 1742 return new Unknown64(machInst); 1743 } else { 1744 if (bits(machInst, 29)) 1745 return new Unknown64(machInst); 1746 uint8_t rmode = bits(machInst, 20, 19); 1747 uint8_t switchVal1 = bits(machInst, 18, 16); 1748 uint8_t switchVal2 = (type << 1) | bits(machInst, 31); 1749 // 30:24=0011110, 21=1, 15:10=000000 1750 switch (switchVal1) { 1751 case 0x0: 1752 switch ((switchVal2 << 2) | rmode) { 1753 case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn) 1754 return new FcvtFpSIntWSN(machInst, rd, rn); 1755 case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn) 1756 return new FcvtFpSIntWSP(machInst, rd, rn); 1757 case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn) 1758 return new FcvtFpSIntWSM(machInst, rd, rn); 1759 case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn) 1760 return new FcvtFpSIntWSZ(machInst, rd, rn); 1761 case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn) 1762 return new FcvtFpSIntXSN(machInst, rd, rn); 1763 case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn) 1764 return new FcvtFpSIntXSP(machInst, rd, rn); 1765 case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn) 1766 return new FcvtFpSIntXSM(machInst, rd, rn); 1767 case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn) 1768 return new FcvtFpSIntXSZ(machInst, rd, rn); 1769 case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn) 1770 return new FcvtFpSIntWDN(machInst, rd, rn); 1771 case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn) 1772 return new FcvtFpSIntWDP(machInst, rd, rn); 1773 case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn) 1774 return new FcvtFpSIntWDM(machInst, rd, rn); 1775 case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn) 1776 return new FcvtFpSIntWDZ(machInst, rd, rn); 1777 case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn) 1778 return new FcvtFpSIntXDN(machInst, rd, rn); 1779 case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn) 1780 return new FcvtFpSIntXDP(machInst, rd, rn); 1781 case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn) 1782 return new FcvtFpSIntXDM(machInst, rd, rn); 1783 case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn) 1784 return new FcvtFpSIntXDZ(machInst, rd, rn); 1785 default: 1786 return new Unknown64(machInst); 1787 } 1788 case 0x1: 1789 switch ((switchVal2 << 2) | rmode) { 1790 case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn) 1791 return new FcvtFpUIntWSN(machInst, rd, rn); 1792 case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn) 1793 return new FcvtFpUIntWSP(machInst, rd, rn); 1794 case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn) 1795 return new FcvtFpUIntWSM(machInst, rd, rn); 1796 case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn) 1797 return new FcvtFpUIntWSZ(machInst, rd, rn); 1798 case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn) 1799 return new FcvtFpUIntXSN(machInst, rd, rn); 1800 case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn) 1801 return new FcvtFpUIntXSP(machInst, rd, rn); 1802 case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn) 1803 return new FcvtFpUIntXSM(machInst, rd, rn); 1804 case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn) 1805 return new FcvtFpUIntXSZ(machInst, rd, rn); 1806 case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn) 1807 return new FcvtFpUIntWDN(machInst, rd, rn); 1808 case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn) 1809 return new FcvtFpUIntWDP(machInst, rd, rn); 1810 case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn) 1811 return new FcvtFpUIntWDM(machInst, rd, rn); 1812 case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn) 1813 return new FcvtFpUIntWDZ(machInst, rd, rn); 1814 case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn) 1815 return new FcvtFpUIntXDN(machInst, rd, rn); 1816 case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn) 1817 return new FcvtFpUIntXDP(machInst, rd, rn); 1818 case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn) 1819 return new FcvtFpUIntXDM(machInst, rd, rn); 1820 case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn) 1821 return new FcvtFpUIntXDZ(machInst, rd, rn); 1822 default: 1823 return new Unknown64(machInst); 1824 } 1825 case 0x2: 1826 if (rmode != 0) 1827 return new Unknown64(machInst); 1828 switch (switchVal2) { 1829 case 0: // SCVTF Sd = convertFromInt(Wn) 1830 return new FcvtWSIntFpS(machInst, rd, rn); 1831 case 1: // SCVTF Sd = convertFromInt(Xn) 1832 return new FcvtXSIntFpS(machInst, rd, rn); 1833 case 2: // SCVTF Dd = convertFromInt(Wn) 1834 return new FcvtWSIntFpD(machInst, rd, rn); 1835 case 3: // SCVTF Dd = convertFromInt(Xn) 1836 return new FcvtXSIntFpD(machInst, rd, rn); 1837 default: 1838 return new Unknown64(machInst); 1839 } 1840 case 0x3: 1841 switch (switchVal2) { 1842 case 0: // UCVTF Sd = convertFromInt(Wn) 1843 return new FcvtWUIntFpS(machInst, rd, rn); 1844 case 1: // UCVTF Sd = convertFromInt(Xn) 1845 return new FcvtXUIntFpS(machInst, rd, rn); 1846 case 2: // UCVTF Dd = convertFromInt(Wn) 1847 return new FcvtWUIntFpD(machInst, rd, rn); 1848 case 3: // UCVTF Dd = convertFromInt(Xn) 1849 return new FcvtXUIntFpD(machInst, rd, rn); 1850 default: 1851 return new Unknown64(machInst); 1852 } 1853 case 0x4: 1854 if (rmode != 0) 1855 return new Unknown64(machInst); 1856 switch (switchVal2) { 1857 case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn) 1858 return new FcvtFpSIntWSA(machInst, rd, rn); 1859 case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn) 1860 return new FcvtFpSIntXSA(machInst, rd, rn); 1861 case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 1862 return new FcvtFpSIntWDA(machInst, rd, rn); 1863 case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 1864 return new FcvtFpSIntXDA(machInst, rd, rn); 1865 default: 1866 return new Unknown64(machInst); 1867 } 1868 case 0x5: 1869 switch (switchVal2) { 1870 case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn) 1871 return new FcvtFpUIntWSA(machInst, rd, rn); 1872 case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn) 1873 return new FcvtFpUIntXSA(machInst, rd, rn); 1874 case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn) 1875 return new FcvtFpUIntWDA(machInst, rd, rn); 1876 case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn) 1877 return new FcvtFpUIntXDA(machInst, rd, rn); 1878 default: 1879 return new Unknown64(machInst); 1880 } 1881 case 0x06: 1882 switch (switchVal2) { 1883 case 0: // FMOV Wd = Sn 1884 if (rmode != 0) 1885 return new Unknown64(machInst); 1886 return new FmovRegCoreW(machInst, rd, rn); 1887 case 3: // FMOV Xd = Dn 1888 if (rmode != 0) 1889 return new Unknown64(machInst); 1890 return new FmovRegCoreX(machInst, rd, rn); 1891 case 5: // FMOV Xd = Vn<127:64> 1892 if (rmode != 1) 1893 return new Unknown64(machInst); 1894 return new FmovURegCoreX(machInst, rd, rn); 1895 default: 1896 return new Unknown64(machInst); 1897 } 1898 break; 1899 case 0x07: 1900 switch (switchVal2) { 1901 case 0: // FMOV Sd = Wn 1902 if (rmode != 0) 1903 return new Unknown64(machInst); 1904 return new FmovCoreRegW(machInst, rd, rn); 1905 case 3: // FMOV Xd = Dn 1906 if (rmode != 0) 1907 return new Unknown64(machInst); 1908 return new FmovCoreRegX(machInst, rd, rn); 1909 case 5: // FMOV Xd = Vn<127:64> 1910 if (rmode != 1) 1911 return new Unknown64(machInst); 1912 return new FmovUCoreRegX(machInst, rd, rn); 1913 default: 1914 return new Unknown64(machInst); 1915 } 1916 break; 1917 default: // Warning! missing cases in switch statement above, that still need to be added 1918 return new Unknown64(machInst); 1919 } 1920 } 1921 M5_UNREACHABLE; 1922 case 0x1: 1923 { 1924 if (bits(machInst, 31) || 1925 bits(machInst, 29) || 1926 bits(machInst, 23)) { 1927 return new Unknown64(machInst); 1928 } 1929 IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16); 1930 IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5); 1931 uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0); 1932 ConditionCode cond = 1933 (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 1934 uint8_t switchVal = (bits(machInst, 4) << 0) | 1935 (bits(machInst, 22) << 1); 1936 // 31:23=000111100, 21=1, 11:10=01 1937 switch (switchVal) { 1938 case 0x0: 1939 // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv 1940 return new FCCmpRegS(machInst, rn, rm, cond, imm); 1941 case 0x1: 1942 // FCCMP flags = if cond then compareSignaling(Sn,Sm) 1943 // else #nzcv 1944 return new FCCmpERegS(machInst, rn, rm, cond, imm); 1945 case 0x2: 1946 // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv 1947 return new FCCmpRegD(machInst, rn, rm, cond, imm); 1948 case 0x3: 1949 // FCCMP flags = if cond then compareSignaling(Dn,Dm) 1950 // else #nzcv 1951 return new FCCmpERegD(machInst, rn, rm, cond, imm); 1952 default: 1953 return new Unknown64(machInst); 1954 } 1955 } 1956 case 0x2: 1957 { 1958 if (bits(machInst, 31) || 1959 bits(machInst, 29) || 1960 bits(machInst, 23)) { 1961 return new Unknown64(machInst); 1962 } 1963 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 1964 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 1965 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 1966 uint8_t switchVal = (bits(machInst, 15, 12) << 0) | 1967 (bits(machInst, 22) << 4); 1968 switch (switchVal) { 1969 case 0x00: // FMUL Sd = Sn * Sm 1970 return new FMulS(machInst, rd, rn, rm); 1971 case 0x10: // FMUL Dd = Dn * Dm 1972 return new FMulD(machInst, rd, rn, rm); 1973 case 0x01: // FDIV Sd = Sn / Sm 1974 return new FDivS(machInst, rd, rn, rm); 1975 case 0x11: // FDIV Dd = Dn / Dm 1976 return new FDivD(machInst, rd, rn, rm); 1977 case 0x02: // FADD Sd = Sn + Sm 1978 return new FAddS(machInst, rd, rn, rm); 1979 case 0x12: // FADD Dd = Dn + Dm 1980 return new FAddD(machInst, rd, rn, rm); 1981 case 0x03: // FSUB Sd = Sn - Sm 1982 return new FSubS(machInst, rd, rn, rm); 1983 case 0x13: // FSUB Dd = Dn - Dm 1984 return new FSubD(machInst, rd, rn, rm); 1985 case 0x04: // FMAX Sd = max(Sn, Sm) 1986 return new FMaxS(machInst, rd, rn, rm); 1987 case 0x14: // FMAX Dd = max(Dn, Dm) 1988 return new FMaxD(machInst, rd, rn, rm); 1989 case 0x05: // FMIN Sd = min(Sn, Sm) 1990 return new FMinS(machInst, rd, rn, rm); 1991 case 0x15: // FMIN Dd = min(Dn, Dm) 1992 return new FMinD(machInst, rd, rn, rm); 1993 case 0x06: // FMAXNM Sd = maxNum(Sn, Sm) 1994 return new FMaxNMS(machInst, rd, rn, rm); 1995 case 0x16: // FMAXNM Dd = maxNum(Dn, Dm) 1996 return new FMaxNMD(machInst, rd, rn, rm); 1997 case 0x07: // FMINNM Sd = minNum(Sn, Sm) 1998 return new FMinNMS(machInst, rd, rn, rm); 1999 case 0x17: // FMINNM Dd = minNum(Dn, Dm) 2000 return new FMinNMD(machInst, rd, rn, rm); 2001 case 0x08: // FNMUL Sd = -(Sn * Sm) 2002 return new FNMulS(machInst, rd, rn, rm); 2003 case 0x18: // FNMUL Dd = -(Dn * Dm) 2004 return new FNMulD(machInst, rd, rn, rm); 2005 default: 2006 return new Unknown64(machInst); 2007 } 2008 } 2009 case 0x3: 2010 { 2011 if (bits(machInst, 31) || bits(machInst, 29)) 2012 return new Unknown64(machInst); 2013 uint8_t type = bits(machInst, 23, 22); 2014 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 2015 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 2016 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 2017 ConditionCode cond = 2018 (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 2019 if (type == 0) // FCSEL Sd = if cond then Sn else Sm 2020 return new FCSelS(machInst, rd, rn, rm, cond); 2021 else if (type == 1) // FCSEL Dd = if cond then Dn else Dm 2022 return new FCSelD(machInst, rd, rn, rm, cond); 2023 else 2024 return new Unknown64(machInst); 2025 } 2026 default: 2027 M5_UNREACHABLE; 2028 } 2029 } 2030 M5_UNREACHABLE; 2031 } 2032} 2033}}; 2034 2035output decoder {{ 2036namespace Aarch64 2037{ 2038 StaticInstPtr 2039 decodeAdvSIMDScalar(ExtMachInst machInst) 2040 { 2041 if (bits(machInst, 24) == 1) { 2042 if (bits(machInst, 10) == 0) { 2043 return decodeNeonScIndexedElem(machInst); 2044 } else if (bits(machInst, 23) == 0) { 2045 return decodeNeonScShiftByImm(machInst); 2046 } 2047 } else if (bits(machInst, 21) == 1) { 2048 if (bits(machInst, 10) == 1) { 2049 return decodeNeonSc3Same(machInst); 2050 } else if (bits(machInst, 11) == 0) { 2051 return decodeNeonSc3Diff(machInst); 2052 } else if (bits(machInst, 20, 17) == 0x0) { 2053 return decodeNeonSc2RegMisc(machInst); 2054 } else if (bits(machInst, 20, 17) == 0x8) { 2055 return decodeNeonScPwise(machInst); 2056 } else { 2057 return new Unknown64(machInst); 2058 } 2059 } else if (bits(machInst, 23, 22) == 0 && 2060 bits(machInst, 15) == 0 && 2061 bits(machInst, 10) == 1) { 2062 return decodeNeonScCopy(machInst); 2063 } else { 2064 return new Unknown64(machInst); 2065 } 2066 return new FailUnimplemented("Unhandled Case6", machInst); 2067 } 2068} 2069}}; 2070 2071output decoder {{ 2072namespace Aarch64 2073{ 2074 template <typename DecoderFeatures> 2075 StaticInstPtr 2076 decodeFpAdvSIMD(ExtMachInst machInst) 2077 { 2078 2079 if (bits(machInst, 28) == 0) { 2080 if (bits(machInst, 31) == 0) { 2081 return decodeAdvSIMD<DecoderFeatures>(machInst); 2082 } else { 2083 return new Unknown64(machInst); 2084 } 2085 } else if (bits(machInst, 30) == 0) { 2086 return decodeFp(machInst); 2087 } else if (bits(machInst, 31) == 0) { 2088 return decodeAdvSIMDScalar(machInst); 2089 } else { 2090 return new Unknown64(machInst); 2091 } 2092 } 2093} 2094}}; 2095 2096let {{ 2097 decoder_output =''' 2098namespace Aarch64 2099{''' 2100 for decoderFlavour, type_dict in decoders.iteritems(): 2101 decoder_output +=''' 2102template StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst); 2103''' % { "df" : decoderFlavour } 2104 decoder_output +=''' 2105}''' 2106}}; 2107 2108output decoder {{ 2109namespace Aarch64 2110{ 2111 StaticInstPtr 2112 decodeGem5Ops(ExtMachInst machInst) 2113 { 2114 const uint32_t m5func = bits(machInst, 23, 16); 2115 switch (m5func) { 2116 case M5OP_ARM: return new Arm(machInst); 2117 case M5OP_QUIESCE: return new Quiesce(machInst); 2118 case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst); 2119 case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst); 2120 case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst); 2121 case M5OP_RPNS: return new Rpns64(machInst); 2122 case M5OP_WAKE_CPU: return new WakeCPU64(machInst); 2123 case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst); 2124 case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst); 2125 case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); 2126 case M5OP_EXIT: return new M5exit64(machInst); 2127 case M5OP_FAIL: return new M5fail64(machInst); 2128 case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); 2129 case M5OP_INIT_PARAM: return new Initparam64(machInst); 2130 case M5OP_RESET_STATS: return new Resetstats64(machInst); 2131 case M5OP_DUMP_STATS: return new Dumpstats64(machInst); 2132 case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst); 2133 case M5OP_CHECKPOINT: return new M5checkpoint64(machInst); 2134 case M5OP_WRITE_FILE: return new M5writefile64(machInst); 2135 case M5OP_READ_FILE: return new M5readfile64(machInst); 2136 case M5OP_DEBUG_BREAK: return new M5break(machInst); 2137 case M5OP_SWITCH_CPU: return new M5switchcpu(machInst); 2138 case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst); 2139 case M5OP_PANIC: return new M5panic(machInst); 2140 case M5OP_WORK_BEGIN: return new M5workbegin64(machInst); 2141 case M5OP_WORK_END: return new M5workend64(machInst); 2142 default: return new Unknown64(machInst); 2143 } 2144 } 2145} 2146}}; 2147 2148def format Aarch64() {{ 2149 decode_block = ''' 2150 { 2151 using namespace Aarch64; 2152 if (bits(machInst, 27) == 0x0) { 2153 if (bits(machInst, 28) == 0x0) 2154 return new Unknown64(machInst); 2155 else if (bits(machInst, 26) == 0) 2156 // bit 28:26=100 2157 return decodeDataProcImm(machInst); 2158 else 2159 // bit 28:26=101 2160 return decodeBranchExcSys(machInst); 2161 } else if (bits(machInst, 25) == 0) { 2162 // bit 27=1, 25=0 2163 return decodeLoadsStores(machInst); 2164 } else if (bits(machInst, 26) == 0) { 2165 // bit 27:25=101 2166 return decodeDataProcReg(machInst); 2167 } else if (bits(machInst, 24) == 1 && 2168 bits(machInst, 31, 28) == 0xF) { 2169 return decodeGem5Ops(machInst); 2170 } else { 2171 // bit 27:25=111 2172 switch(decoderFlavour){ 2173 default: 2174 return decodeFpAdvSIMD<GenericDecoder>(machInst); 2175 } 2176 } 2177 } 2178 ''' 2179}}; 2180