xref: /gem5/src/arch/arm/isa/bitfields.isa

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// Copyright (c) 2007-2008 The Florida State University
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// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//

// Opcode fields
def bitfield ENCODING      encoding;
def bitfield OPCODE        opcode;
def bitfield MEDIA_OPCODE  mediaOpcode;
def bitfield MEDIA_OPCODE2 mediaOpcode2;
def bitfield USEIMM        useImm;
def bitfield OPCODE_24     opcode24;
def bitfield OPCODE_23_20  opcode23_20;
def bitfield OPCODE_23_21  opcode23_21;
def bitfield OPCODE_22     opcode22;
def bitfield OPCODE_20     opcode20;
def bitfield OPCODE_19_16  opcode19_16;
def bitfield OPCODE_19     opcode19;
def bitfield OPCODE_18     opcode18;
def bitfield OPCODE_15_12  opcode15_12;
def bitfield OPCODE_15     opcode15;
def bitfield MISC_OPCODE   miscOpcode;
def bitfield OPC2          opc2; 
def bitfield OPCODE_7      opcode7;
def bitfield OPCODE_6      opcode6;
def bitfield OPCODE_4      opcode4;

def bitfield IS_MISC       isMisc;
def bitfield SEVEN_AND_FOUR sevenAndFour;

def bitfield THUMB         thumb;
def bitfield BIGTHUMB      bigThumb;

// Other
def bitfield COND_CODE     condCode;
def bitfield S_FIELD       sField;
def bitfield RN            rn;
def bitfield RD            rd;
def bitfield SHIFT_SIZE    shiftSize;
def bitfield SHIFT         shift;
def bitfield RM            rm;

def bitfield RS            rs;

def bitfield PUSWL         puswl;
def bitfield PREPOST       puswl.prepost;
def bitfield UP               puswl.up;
def bitfield PSRUSER       puswl.psruser;
def bitfield WRITEBACK     puswl.writeback;
def bitfield LOADOP        puswl.loadOp;

def bitfield PUBWL         pubwl;

def bitfield IMM           imm;

def bitfield IMMED_11_0    immed11_0;

def bitfield IMMED_HI_11_8 immedHi11_8;
def bitfield IMMED_LO_3_0  immedLo3_0;

def bitfield IMMED_23_0    immed23_0;

def bitfield CPNUM         cpNum;
// Note that FP Regs are only 3 bits
def bitfield FN            fn;
def bitfield FD            fd;
def bitfield FPREGIMM      fpRegImm;
// We can just use 3:0 for FM since the hard-wired FP regs are handled in
// float_regfile.hh
def bitfield FM            fm;
def bitfield FPIMM         fpImm;
def bitfield PUNWL         punwl;

// M5 instructions
def bitfield M5FUNC        m5Func;

// Thumb bitfields
def bitfield TOPCODE_15_13  topcode15_13;
def bitfield TOPCODE_13_11  topcode13_11;
def bitfield TOPCODE_12_11  topcode12_11;
def bitfield TOPCODE_12_10  topcode12_10;
def bitfield TOPCODE_11_9   topcode11_9;
def bitfield TOPCODE_11_8   topcode11_8;
def bitfield TOPCODE_10_9   topcode10_9;
def bitfield TOPCODE_10_8   topcode10_8;
def bitfield TOPCODE_9_6    topcode9_6;
def bitfield TOPCODE_7      topcode7;
def bitfield TOPCODE_7_6    topcode7_6;
def bitfield TOPCODE_7_5    topcode7_5;
def bitfield TOPCODE_7_4    topcode7_4;
def bitfield TOPCODE_3_0    topcode3_0;