isa.hh revision 7733:08d6a773d1b6
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2010 ARM Limited 312855Sgabeblack@google.com * All rights reserved 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * The license below extends only to copyright in the software and shall 612855Sgabeblack@google.com * not be construed as granting a license to any other intellectual 712855Sgabeblack@google.com * property including but not limited to intellectual property relating 812855Sgabeblack@google.com * to a hardware implementation of the functionality of the software 912855Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1012855Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1112855Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1212855Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1312855Sgabeblack@google.com * 1412855Sgabeblack@google.com * Copyright (c) 2009 The Regents of The University of Michigan 1512855Sgabeblack@google.com * All rights reserved. 1612855Sgabeblack@google.com * 1712855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1812855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 1912855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2112855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2212855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2312855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2412855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2512855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2612855Sgabeblack@google.com * this software without specific prior written permission. 2712855Sgabeblack@google.com * 2812855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912855Sgabeblack@google.com * 4012855Sgabeblack@google.com * Authors: Gabe Black 4112855Sgabeblack@google.com */ 4212855Sgabeblack@google.com 4312855Sgabeblack@google.com#ifndef __ARCH_ARM_ISA_HH__ 4412855Sgabeblack@google.com#define __ARCH_ARM_ISA_HH__ 4512855Sgabeblack@google.com 4612855Sgabeblack@google.com#include "arch/arm/registers.hh" 4712855Sgabeblack@google.com#include "arch/arm/tlb.hh" 4812855Sgabeblack@google.com#include "arch/arm/types.hh" 4912855Sgabeblack@google.com 5012855Sgabeblack@google.comclass ThreadContext; 5112855Sgabeblack@google.comclass Checkpoint; 5212855Sgabeblack@google.comclass EventManager; 5312855Sgabeblack@google.com 5412855Sgabeblack@google.comnamespace ArmISA 5512855Sgabeblack@google.com{ 5612855Sgabeblack@google.com class ISA 5712855Sgabeblack@google.com { 5812855Sgabeblack@google.com protected: 5912855Sgabeblack@google.com MiscReg miscRegs[NumMiscRegs]; 6012855Sgabeblack@google.com const IntRegIndex *intRegMap; 6112855Sgabeblack@google.com 6212855Sgabeblack@google.com void 6312855Sgabeblack@google.com updateRegMap(CPSR cpsr) 6412855Sgabeblack@google.com { 6512855Sgabeblack@google.com switch (cpsr.mode) { 6612855Sgabeblack@google.com case MODE_USER: 6712855Sgabeblack@google.com case MODE_SYSTEM: 6812855Sgabeblack@google.com intRegMap = IntRegUsrMap; 69 break; 70 case MODE_FIQ: 71 intRegMap = IntRegFiqMap; 72 break; 73 case MODE_IRQ: 74 intRegMap = IntRegIrqMap; 75 break; 76 case MODE_SVC: 77 intRegMap = IntRegSvcMap; 78 break; 79 case MODE_MON: 80 intRegMap = IntRegMonMap; 81 break; 82 case MODE_ABORT: 83 intRegMap = IntRegAbtMap; 84 break; 85 case MODE_UNDEFINED: 86 intRegMap = IntRegUndMap; 87 break; 88 default: 89 panic("Unrecognized mode setting in CPSR.\n"); 90 } 91 } 92 93 public: 94 void clear(); 95 96 MiscReg readMiscRegNoEffect(int misc_reg); 97 MiscReg readMiscReg(int misc_reg, ThreadContext *tc); 98 void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 99 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc); 100 101 int 102 flattenIntIndex(int reg) 103 { 104 assert(reg >= 0); 105 if (reg < NUM_ARCH_INTREGS) { 106 return intRegMap[reg]; 107 } else if (reg < NUM_INTREGS) { 108 return reg; 109 } else { 110 int mode = reg / intRegsPerMode; 111 reg = reg % intRegsPerMode; 112 switch (mode) { 113 case MODE_USER: 114 case MODE_SYSTEM: 115 return INTREG_USR(reg); 116 case MODE_FIQ: 117 return INTREG_FIQ(reg); 118 case MODE_IRQ: 119 return INTREG_IRQ(reg); 120 case MODE_SVC: 121 return INTREG_SVC(reg); 122 case MODE_MON: 123 return INTREG_MON(reg); 124 case MODE_ABORT: 125 return INTREG_ABT(reg); 126 case MODE_UNDEFINED: 127 return INTREG_UND(reg); 128 default: 129 panic("Flattening into an unknown mode.\n"); 130 } 131 } 132 } 133 134 int 135 flattenFloatIndex(int reg) 136 { 137 return reg; 138 } 139 140 int 141 flattenMiscIndex(int reg) 142 { 143 if (reg == MISCREG_SPSR) { 144 int spsr_idx = NUM_MISCREGS; 145 CPSR cpsr = miscRegs[MISCREG_CPSR]; 146 switch (cpsr.mode) { 147 case MODE_USER: 148 warn("User mode does not have SPSR\n"); 149 spsr_idx = MISCREG_SPSR; 150 break; 151 case MODE_FIQ: 152 spsr_idx = MISCREG_SPSR_FIQ; 153 break; 154 case MODE_IRQ: 155 spsr_idx = MISCREG_SPSR_IRQ; 156 break; 157 case MODE_SVC: 158 spsr_idx = MISCREG_SPSR_SVC; 159 break; 160 case MODE_MON: 161 spsr_idx = MISCREG_SPSR_MON; 162 break; 163 case MODE_ABORT: 164 spsr_idx = MISCREG_SPSR_ABT; 165 break; 166 case MODE_UNDEFINED: 167 spsr_idx = MISCREG_SPSR_UND; 168 break; 169 default: 170 warn("Trying to access SPSR in an invalid mode: %d\n", 171 cpsr.mode); 172 spsr_idx = MISCREG_SPSR; 173 break; 174 } 175 return spsr_idx; 176 } 177 return reg; 178 } 179 180 void serialize(EventManager *em, std::ostream &os) 181 { 182 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); 183 SERIALIZE_ARRAY(miscRegs, NumMiscRegs); 184 } 185 void unserialize(EventManager *em, Checkpoint *cp, 186 const std::string §ion) 187 { 188 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); 189 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs); 190 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; 191 updateRegMap(tmp_cpsr); 192 } 193 194 ISA() 195 { 196 SCTLR sctlr; 197 sctlr = 0; 198 miscRegs[MISCREG_SCTLR_RST] = sctlr; 199 200 clear(); 201 } 202 }; 203} 204 205#endif 206