isa.hh revision 7390:90824865d8e6 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{
55    class ISA
56    {
57      protected:
58        MiscReg miscRegs[NumMiscRegs];
59        const IntRegIndex *intRegMap;
60
61        void
62        updateRegMap(CPSR cpsr)
63        {
64            switch (cpsr.mode) {
65              case MODE_USER:
66              case MODE_SYSTEM:
67                intRegMap = IntRegUsrMap;
68                break;
69              case MODE_FIQ:
70                intRegMap = IntRegFiqMap;
71                break;
72              case MODE_IRQ:
73                intRegMap = IntRegIrqMap;
74                break;
75              case MODE_SVC:
76                intRegMap = IntRegSvcMap;
77                break;
78              case MODE_MON:
79                intRegMap = IntRegMonMap;
80                break;
81              case MODE_ABORT:
82                intRegMap = IntRegAbtMap;
83                break;
84              case MODE_UNDEFINED:
85                intRegMap = IntRegUndMap;
86                break;
87              default:
88                panic("Unrecognized mode setting in CPSR.\n");
89            }
90        }
91
92      public:
93        void clear()
94        {
95            memset(miscRegs, 0, sizeof(miscRegs));
96            CPSR cpsr = 0;
97            cpsr.mode = MODE_USER;
98            miscRegs[MISCREG_CPSR] = cpsr;
99            updateRegMap(cpsr);
100
101            SCTLR sctlr = 0;
102            sctlr.nmfi = 1;
103            sctlr.rao1 = 1;
104            sctlr.rao2 = 1;
105            sctlr.rao3 = 1;
106            sctlr.rao4 = 1;
107            miscRegs[MISCREG_SCTLR] = sctlr;
108
109            /*
110             * Technically this should be 0, but we don't support those
111             * settings.
112             */
113            CPACR cpacr = 0;
114            // Enable CP 10, 11
115            cpacr.cp10 = 0x3;
116            cpacr.cp11 = 0x3;
117            miscRegs[MISCREG_CPACR] = cpacr;
118
119            /* Start with an event in the mailbox */
120            miscRegs[MISCREG_SEV_MAILBOX] = 1;
121
122            /*
123             * Implemented = '5' from "M5",
124             * Variant = 0,
125             */
126            miscRegs[MISCREG_MIDR] =
127                (0x35 << 24) | //Implementor is '5' from "M5"
128                (0 << 20)    | //Variant
129                (0xf << 16)  | //Architecture from CPUID scheme
130                (0 << 4)     | //Primary part number
131                (0 << 0)     | //Revision
132                0;
133
134            // Separate Instruction and Data TLBs.
135            miscRegs[MISCREG_TLBTR] = 1;
136
137            MVFR0 mvfr0 = 0;
138            mvfr0.advSimdRegisters = 2;
139            mvfr0.singlePrecision = 2;
140            mvfr0.doublePrecision = 2;
141            mvfr0.vfpExceptionTrapping = 0;
142            mvfr0.divide = 1;
143            mvfr0.squareRoot = 1;
144            mvfr0.shortVectors = 1;
145            mvfr0.roundingModes = 1;
146            miscRegs[MISCREG_MVFR0] = mvfr0;
147
148            MVFR1 mvfr1 = 0;
149            mvfr1.flushToZero = 1;
150            mvfr1.defaultNaN = 1;
151            mvfr1.advSimdLoadStore = 1;
152            mvfr1.advSimdInteger = 1;
153            mvfr1.advSimdSinglePrecision = 1;
154            mvfr1.advSimdHalfPrecision = 1;
155            mvfr1.vfpHalfPrecision = 1;
156            miscRegs[MISCREG_MVFR1] = mvfr1;
157
158            miscRegs[MISCREG_MPIDR] = 0;
159
160            //XXX We need to initialize the rest of the state.
161        }
162
163        MiscReg
164        readMiscRegNoEffect(int misc_reg)
165        {
166            assert(misc_reg < NumMiscRegs);
167            if (misc_reg == MISCREG_SPSR) {
168                CPSR cpsr = miscRegs[MISCREG_CPSR];
169                switch (cpsr.mode) {
170                  case MODE_USER:
171                    return miscRegs[MISCREG_SPSR];
172                  case MODE_FIQ:
173                    return miscRegs[MISCREG_SPSR_FIQ];
174                  case MODE_IRQ:
175                    return miscRegs[MISCREG_SPSR_IRQ];
176                  case MODE_SVC:
177                    return miscRegs[MISCREG_SPSR_SVC];
178                  case MODE_MON:
179                    return miscRegs[MISCREG_SPSR_MON];
180                  case MODE_ABORT:
181                    return miscRegs[MISCREG_SPSR_ABT];
182                  case MODE_UNDEFINED:
183                    return miscRegs[MISCREG_SPSR_UND];
184                  default:
185                    return miscRegs[MISCREG_SPSR];
186                }
187            }
188            return miscRegs[misc_reg];
189        }
190
191        MiscReg
192        readMiscReg(int misc_reg, ThreadContext *tc)
193        {
194            if (misc_reg == MISCREG_CPSR) {
195                CPSR cpsr = miscRegs[misc_reg];
196                Addr pc = tc->readPC();
197                if (pc & (ULL(1) << PcJBitShift))
198                    cpsr.j = 1;
199                else
200                    cpsr.j = 0;
201                if (pc & (ULL(1) << PcTBitShift))
202                    cpsr.t = 1;
203                else
204                    cpsr.t = 0;
205                return cpsr;
206            }
207            if (misc_reg >= MISCREG_CP15_UNIMP_START &&
208                misc_reg < MISCREG_CP15_END) {
209                panic("Unimplemented CP15 register %s read.\n",
210                      miscRegName[misc_reg]);
211            }
212            switch (misc_reg) {
213              case MISCREG_CLIDR:
214                warn("The clidr register always reports 0 caches.\n");
215                break;
216              case MISCREG_CCSIDR:
217                warn("The ccsidr register isn't implemented and "
218                        "always reads as 0.\n");
219                break;
220            }
221            return readMiscRegNoEffect(misc_reg);
222        }
223
224        void
225        setMiscRegNoEffect(int misc_reg, const MiscReg &val)
226        {
227            assert(misc_reg < NumMiscRegs);
228            if (misc_reg == MISCREG_SPSR) {
229                CPSR cpsr = miscRegs[MISCREG_CPSR];
230                switch (cpsr.mode) {
231                  case MODE_USER:
232                    miscRegs[MISCREG_SPSR] = val;
233                    return;
234                  case MODE_FIQ:
235                    miscRegs[MISCREG_SPSR_FIQ] = val;
236                    return;
237                  case MODE_IRQ:
238                    miscRegs[MISCREG_SPSR_IRQ] = val;
239                    return;
240                  case MODE_SVC:
241                    miscRegs[MISCREG_SPSR_SVC] = val;
242                    return;
243                  case MODE_MON:
244                    miscRegs[MISCREG_SPSR_MON] = val;
245                    return;
246                  case MODE_ABORT:
247                    miscRegs[MISCREG_SPSR_ABT] = val;
248                    return;
249                  case MODE_UNDEFINED:
250                    miscRegs[MISCREG_SPSR_UND] = val;
251                    return;
252                  default:
253                    miscRegs[MISCREG_SPSR] = val;
254                    return;
255                }
256            }
257            miscRegs[misc_reg] = val;
258        }
259
260        void
261        setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
262        {
263            MiscReg newVal = val;
264            if (misc_reg == MISCREG_CPSR) {
265                updateRegMap(val);
266                CPSR cpsr = val;
267                DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
268                        cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
269                Addr npc = tc->readNextPC() & ~PcModeMask;
270                if (cpsr.j)
271                    npc = npc | (ULL(1) << PcJBitShift);
272                if (cpsr.t)
273                    npc = npc | (ULL(1) << PcTBitShift);
274
275                tc->setNextPC(npc);
276            }
277            if (misc_reg >= MISCREG_CP15_UNIMP_START &&
278                misc_reg < MISCREG_CP15_END) {
279                panic("Unimplemented CP15 register %s wrote with %#x.\n",
280                      miscRegName[misc_reg], val);
281            }
282            switch (misc_reg) {
283              case MISCREG_CPACR:
284                {
285                    CPACR newCpacr = 0;
286                    CPACR valCpacr = val;
287                    newCpacr.cp10 = valCpacr.cp10;
288                    newCpacr.cp11 = valCpacr.cp11;
289                    if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
290                        panic("Disabling coprocessors isn't implemented.\n");
291                    }
292                    newVal = newCpacr;
293                }
294                break;
295              case MISCREG_CSSELR:
296                warn("The csselr register isn't implemented.\n");
297                break;
298              case MISCREG_TLBTR:
299              case MISCREG_MVFR0:
300              case MISCREG_MVFR1:
301              case MISCREG_MPIDR:
302                return;
303            }
304            return setMiscRegNoEffect(misc_reg, newVal);
305        }
306
307        int
308        flattenIntIndex(int reg)
309        {
310            assert(reg >= 0);
311            if (reg < NUM_ARCH_INTREGS) {
312                return intRegMap[reg];
313            } else if (reg < NUM_INTREGS) {
314                return reg;
315            } else {
316                int mode = reg / intRegsPerMode;
317                reg = reg % intRegsPerMode;
318                switch (mode) {
319                  case MODE_USER:
320                  case MODE_SYSTEM:
321                    return INTREG_USR(reg);
322                  case MODE_FIQ:
323                    return INTREG_FIQ(reg);
324                  case MODE_IRQ:
325                    return INTREG_IRQ(reg);
326                  case MODE_SVC:
327                    return INTREG_SVC(reg);
328                  case MODE_MON:
329                    return INTREG_MON(reg);
330                  case MODE_ABORT:
331                    return INTREG_ABT(reg);
332                  case MODE_UNDEFINED:
333                    return INTREG_UND(reg);
334                  default:
335                    panic("Flattening into an unknown mode.\n");
336                }
337            }
338        }
339
340        int
341        flattenFloatIndex(int reg)
342        {
343            return reg;
344        }
345
346        void serialize(EventManager *em, std::ostream &os)
347        {}
348        void unserialize(EventManager *em, Checkpoint *cp,
349                const std::string &section)
350        {}
351
352        ISA()
353        {
354            clear();
355        }
356    };
357}
358
359#endif
360