intregs.hh revision 8902 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include <cassert>
44
45#ifndef __ARCH_ARM_INTREGS_HH__
46#define __ARCH_ARM_INTREGS_HH__
47
48#include "arch/arm/types.hh"
49
50namespace ArmISA
51{
52
53enum IntRegIndex
54{
55    /* All the unique register indices. */
56    INTREG_R0,
57    INTREG_R1,
58    INTREG_R2,
59    INTREG_R3,
60    INTREG_R4,
61    INTREG_R5,
62    INTREG_R6,
63    INTREG_R7,
64    INTREG_R8,
65    INTREG_R9,
66    INTREG_R10,
67    INTREG_R11,
68    INTREG_R12,
69    INTREG_R13,
70    INTREG_SP = INTREG_R13,
71    INTREG_R14,
72    INTREG_LR = INTREG_R14,
73    INTREG_R15,
74    INTREG_PC = INTREG_R15,
75
76    INTREG_R13_SVC,
77    INTREG_SP_SVC = INTREG_R13_SVC,
78    INTREG_R14_SVC,
79    INTREG_LR_SVC = INTREG_R14_SVC,
80
81    INTREG_R13_MON,
82    INTREG_SP_MON = INTREG_R13_MON,
83    INTREG_R14_MON,
84    INTREG_LR_MON = INTREG_R14_MON,
85
86    INTREG_R13_ABT,
87    INTREG_SP_ABT = INTREG_R13_ABT,
88    INTREG_R14_ABT,
89    INTREG_LR_ABT = INTREG_R14_ABT,
90
91    INTREG_R13_UND,
92    INTREG_SP_UND = INTREG_R13_UND,
93    INTREG_R14_UND,
94    INTREG_LR_UND = INTREG_R14_UND,
95
96    INTREG_R13_IRQ,
97    INTREG_SP_IRQ = INTREG_R13_IRQ,
98    INTREG_R14_IRQ,
99    INTREG_LR_IRQ = INTREG_R14_IRQ,
100
101    INTREG_R8_FIQ,
102    INTREG_R9_FIQ,
103    INTREG_R10_FIQ,
104    INTREG_R11_FIQ,
105    INTREG_R12_FIQ,
106    INTREG_R13_FIQ,
107    INTREG_SP_FIQ = INTREG_R13_FIQ,
108    INTREG_R14_FIQ,
109    INTREG_LR_FIQ = INTREG_R14_FIQ,
110
111    INTREG_ZERO, // Dummy zero reg since there has to be one.
112    INTREG_UREG0,
113    INTREG_UREG1,
114    INTREG_UREG2,
115    INTREG_CONDCODES_NZ,
116    INTREG_CONDCODES_C,
117    INTREG_CONDCODES_V,
118    INTREG_CONDCODES_GE,
119    INTREG_FPCONDCODES,
120
121    NUM_INTREGS,
122    NUM_ARCH_INTREGS = INTREG_PC + 1,
123
124    /* All the aliased indexes. */
125
126    /* USR mode */
127    INTREG_R0_USR = INTREG_R0,
128    INTREG_R1_USR = INTREG_R1,
129    INTREG_R2_USR = INTREG_R2,
130    INTREG_R3_USR = INTREG_R3,
131    INTREG_R4_USR = INTREG_R4,
132    INTREG_R5_USR = INTREG_R5,
133    INTREG_R6_USR = INTREG_R6,
134    INTREG_R7_USR = INTREG_R7,
135    INTREG_R8_USR = INTREG_R8,
136    INTREG_R9_USR = INTREG_R9,
137    INTREG_R10_USR = INTREG_R10,
138    INTREG_R11_USR = INTREG_R11,
139    INTREG_R12_USR = INTREG_R12,
140    INTREG_R13_USR = INTREG_R13,
141    INTREG_SP_USR = INTREG_SP,
142    INTREG_R14_USR = INTREG_R14,
143    INTREG_LR_USR = INTREG_LR,
144    INTREG_R15_USR = INTREG_R15,
145    INTREG_PC_USR = INTREG_PC,
146
147    /* SVC mode */
148    INTREG_R0_SVC = INTREG_R0,
149    INTREG_R1_SVC = INTREG_R1,
150    INTREG_R2_SVC = INTREG_R2,
151    INTREG_R3_SVC = INTREG_R3,
152    INTREG_R4_SVC = INTREG_R4,
153    INTREG_R5_SVC = INTREG_R5,
154    INTREG_R6_SVC = INTREG_R6,
155    INTREG_R7_SVC = INTREG_R7,
156    INTREG_R8_SVC = INTREG_R8,
157    INTREG_R9_SVC = INTREG_R9,
158    INTREG_R10_SVC = INTREG_R10,
159    INTREG_R11_SVC = INTREG_R11,
160    INTREG_R12_SVC = INTREG_R12,
161    INTREG_PC_SVC = INTREG_PC,
162    INTREG_R15_SVC = INTREG_R15,
163
164    /* MON mode */
165    INTREG_R0_MON = INTREG_R0,
166    INTREG_R1_MON = INTREG_R1,
167    INTREG_R2_MON = INTREG_R2,
168    INTREG_R3_MON = INTREG_R3,
169    INTREG_R4_MON = INTREG_R4,
170    INTREG_R5_MON = INTREG_R5,
171    INTREG_R6_MON = INTREG_R6,
172    INTREG_R7_MON = INTREG_R7,
173    INTREG_R8_MON = INTREG_R8,
174    INTREG_R9_MON = INTREG_R9,
175    INTREG_R10_MON = INTREG_R10,
176    INTREG_R11_MON = INTREG_R11,
177    INTREG_R12_MON = INTREG_R12,
178    INTREG_PC_MON = INTREG_PC,
179    INTREG_R15_MON = INTREG_R15,
180
181    /* ABT mode */
182    INTREG_R0_ABT = INTREG_R0,
183    INTREG_R1_ABT = INTREG_R1,
184    INTREG_R2_ABT = INTREG_R2,
185    INTREG_R3_ABT = INTREG_R3,
186    INTREG_R4_ABT = INTREG_R4,
187    INTREG_R5_ABT = INTREG_R5,
188    INTREG_R6_ABT = INTREG_R6,
189    INTREG_R7_ABT = INTREG_R7,
190    INTREG_R8_ABT = INTREG_R8,
191    INTREG_R9_ABT = INTREG_R9,
192    INTREG_R10_ABT = INTREG_R10,
193    INTREG_R11_ABT = INTREG_R11,
194    INTREG_R12_ABT = INTREG_R12,
195    INTREG_PC_ABT = INTREG_PC,
196    INTREG_R15_ABT = INTREG_R15,
197
198    /* UND mode */
199    INTREG_R0_UND = INTREG_R0,
200    INTREG_R1_UND = INTREG_R1,
201    INTREG_R2_UND = INTREG_R2,
202    INTREG_R3_UND = INTREG_R3,
203    INTREG_R4_UND = INTREG_R4,
204    INTREG_R5_UND = INTREG_R5,
205    INTREG_R6_UND = INTREG_R6,
206    INTREG_R7_UND = INTREG_R7,
207    INTREG_R8_UND = INTREG_R8,
208    INTREG_R9_UND = INTREG_R9,
209    INTREG_R10_UND = INTREG_R10,
210    INTREG_R11_UND = INTREG_R11,
211    INTREG_R12_UND = INTREG_R12,
212    INTREG_PC_UND = INTREG_PC,
213    INTREG_R15_UND = INTREG_R15,
214
215    /* IRQ mode */
216    INTREG_R0_IRQ = INTREG_R0,
217    INTREG_R1_IRQ = INTREG_R1,
218    INTREG_R2_IRQ = INTREG_R2,
219    INTREG_R3_IRQ = INTREG_R3,
220    INTREG_R4_IRQ = INTREG_R4,
221    INTREG_R5_IRQ = INTREG_R5,
222    INTREG_R6_IRQ = INTREG_R6,
223    INTREG_R7_IRQ = INTREG_R7,
224    INTREG_R8_IRQ = INTREG_R8,
225    INTREG_R9_IRQ = INTREG_R9,
226    INTREG_R10_IRQ = INTREG_R10,
227    INTREG_R11_IRQ = INTREG_R11,
228    INTREG_R12_IRQ = INTREG_R12,
229    INTREG_PC_IRQ = INTREG_PC,
230    INTREG_R15_IRQ = INTREG_R15,
231
232    /* FIQ mode */
233    INTREG_R0_FIQ = INTREG_R0,
234    INTREG_R1_FIQ = INTREG_R1,
235    INTREG_R2_FIQ = INTREG_R2,
236    INTREG_R3_FIQ = INTREG_R3,
237    INTREG_R4_FIQ = INTREG_R4,
238    INTREG_R5_FIQ = INTREG_R5,
239    INTREG_R6_FIQ = INTREG_R6,
240    INTREG_R7_FIQ = INTREG_R7,
241    INTREG_PC_FIQ = INTREG_PC,
242    INTREG_R15_FIQ = INTREG_R15
243};
244
245typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
246
247const IntRegMap IntRegUsrMap = {
248    INTREG_R0_USR,  INTREG_R1_USR,  INTREG_R2_USR,  INTREG_R3_USR,
249    INTREG_R4_USR,  INTREG_R5_USR,  INTREG_R6_USR,  INTREG_R7_USR,
250    INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
251    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
252};
253
254static inline IntRegIndex
255INTREG_USR(unsigned index)
256{
257    assert(index < NUM_ARCH_INTREGS);
258    return IntRegUsrMap[index];
259}
260
261const IntRegMap IntRegSvcMap = {
262    INTREG_R0_SVC,  INTREG_R1_SVC,  INTREG_R2_SVC,  INTREG_R3_SVC,
263    INTREG_R4_SVC,  INTREG_R5_SVC,  INTREG_R6_SVC,  INTREG_R7_SVC,
264    INTREG_R8_SVC,  INTREG_R9_SVC,  INTREG_R10_SVC, INTREG_R11_SVC,
265    INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
266};
267
268static inline IntRegIndex
269INTREG_SVC(unsigned index)
270{
271    assert(index < NUM_ARCH_INTREGS);
272    return IntRegSvcMap[index];
273}
274
275const IntRegMap IntRegMonMap = {
276    INTREG_R0_MON,  INTREG_R1_MON,  INTREG_R2_MON,  INTREG_R3_MON,
277    INTREG_R4_MON,  INTREG_R5_MON,  INTREG_R6_MON,  INTREG_R7_MON,
278    INTREG_R8_MON,  INTREG_R9_MON,  INTREG_R10_MON, INTREG_R11_MON,
279    INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
280};
281
282static inline IntRegIndex
283INTREG_MON(unsigned index)
284{
285    assert(index < NUM_ARCH_INTREGS);
286    return IntRegMonMap[index];
287}
288
289const IntRegMap IntRegAbtMap = {
290    INTREG_R0_ABT,  INTREG_R1_ABT,  INTREG_R2_ABT,  INTREG_R3_ABT,
291    INTREG_R4_ABT,  INTREG_R5_ABT,  INTREG_R6_ABT,  INTREG_R7_ABT,
292    INTREG_R8_ABT,  INTREG_R9_ABT,  INTREG_R10_ABT, INTREG_R11_ABT,
293    INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
294};
295
296static inline IntRegIndex
297INTREG_ABT(unsigned index)
298{
299    assert(index < NUM_ARCH_INTREGS);
300    return IntRegAbtMap[index];
301}
302
303const IntRegMap IntRegUndMap = {
304    INTREG_R0_UND,  INTREG_R1_UND,  INTREG_R2_UND,  INTREG_R3_UND,
305    INTREG_R4_UND,  INTREG_R5_UND,  INTREG_R6_UND,  INTREG_R7_UND,
306    INTREG_R8_UND,  INTREG_R9_UND,  INTREG_R10_UND, INTREG_R11_UND,
307    INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
308};
309
310static inline IntRegIndex
311INTREG_UND(unsigned index)
312{
313    assert(index < NUM_ARCH_INTREGS);
314    return IntRegUndMap[index];
315}
316
317const IntRegMap IntRegIrqMap = {
318    INTREG_R0_IRQ,  INTREG_R1_IRQ,  INTREG_R2_IRQ,  INTREG_R3_IRQ,
319    INTREG_R4_IRQ,  INTREG_R5_IRQ,  INTREG_R6_IRQ,  INTREG_R7_IRQ,
320    INTREG_R8_IRQ,  INTREG_R9_IRQ,  INTREG_R10_IRQ, INTREG_R11_IRQ,
321    INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
322};
323
324static inline IntRegIndex
325INTREG_IRQ(unsigned index)
326{
327    assert(index < NUM_ARCH_INTREGS);
328    return IntRegIrqMap[index];
329}
330
331const IntRegMap IntRegFiqMap = {
332    INTREG_R0_FIQ,  INTREG_R1_FIQ,  INTREG_R2_FIQ,  INTREG_R3_FIQ,
333    INTREG_R4_FIQ,  INTREG_R5_FIQ,  INTREG_R6_FIQ,  INTREG_R7_FIQ,
334    INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
335    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
336};
337
338static inline IntRegIndex
339INTREG_FIQ(unsigned index)
340{
341    assert(index < NUM_ARCH_INTREGS);
342    return IntRegFiqMap[index];
343}
344
345static const unsigned intRegsPerMode = NUM_INTREGS;
346
347static inline int
348intRegInMode(OperatingMode mode, int reg)
349{
350    assert(reg < NUM_ARCH_INTREGS);
351    return mode * intRegsPerMode + reg;
352}
353
354}
355
356#endif
357