intregs.hh revision 8302:9f23d01421de
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#include <cassert> 44 45#ifndef __ARCH_ARM_INTREGS_HH__ 46#define __ARCH_ARM_INTREGS_HH__ 47 48#include "arch/arm/types.hh" 49 50namespace ArmISA 51{ 52 53enum IntRegIndex 54{ 55 /* All the unique register indices. */ 56 INTREG_R0, 57 INTREG_R1, 58 INTREG_R2, 59 INTREG_R3, 60 INTREG_R4, 61 INTREG_R5, 62 INTREG_R6, 63 INTREG_R7, 64 INTREG_R8, 65 INTREG_R9, 66 INTREG_R10, 67 INTREG_R11, 68 INTREG_R12, 69 INTREG_R13, 70 INTREG_SP = INTREG_R13, 71 INTREG_R14, 72 INTREG_LR = INTREG_R14, 73 INTREG_R15, 74 INTREG_PC = INTREG_R15, 75 76 INTREG_R13_SVC, 77 INTREG_SP_SVC = INTREG_R13_SVC, 78 INTREG_R14_SVC, 79 INTREG_LR_SVC = INTREG_R14_SVC, 80 81 INTREG_R13_MON, 82 INTREG_SP_MON = INTREG_R13_MON, 83 INTREG_R14_MON, 84 INTREG_LR_MON = INTREG_R14_MON, 85 86 INTREG_R13_ABT, 87 INTREG_SP_ABT = INTREG_R13_ABT, 88 INTREG_R14_ABT, 89 INTREG_LR_ABT = INTREG_R14_ABT, 90 91 INTREG_R13_UND, 92 INTREG_SP_UND = INTREG_R13_UND, 93 INTREG_R14_UND, 94 INTREG_LR_UND = INTREG_R14_UND, 95 96 INTREG_R13_IRQ, 97 INTREG_SP_IRQ = INTREG_R13_IRQ, 98 INTREG_R14_IRQ, 99 INTREG_LR_IRQ = INTREG_R14_IRQ, 100 101 INTREG_R8_FIQ, 102 INTREG_R9_FIQ, 103 INTREG_R10_FIQ, 104 INTREG_R11_FIQ, 105 INTREG_R12_FIQ, 106 INTREG_R13_FIQ, 107 INTREG_SP_FIQ = INTREG_R13_FIQ, 108 INTREG_R14_FIQ, 109 INTREG_LR_FIQ = INTREG_R14_FIQ, 110 111 INTREG_ZERO, // Dummy zero reg since there has to be one. 112 INTREG_UREG0, 113 INTREG_UREG1, 114 INTREG_UREG2, 115 INTREG_CONDCODES_F, 116 INTREG_CONDCODES_GE, 117 INTREG_FPCONDCODES, 118 119 NUM_INTREGS, 120 NUM_ARCH_INTREGS = INTREG_PC + 1, 121 122 /* All the aliased indexes. */ 123 124 /* USR mode */ 125 INTREG_R0_USR = INTREG_R0, 126 INTREG_R1_USR = INTREG_R1, 127 INTREG_R2_USR = INTREG_R2, 128 INTREG_R3_USR = INTREG_R3, 129 INTREG_R4_USR = INTREG_R4, 130 INTREG_R5_USR = INTREG_R5, 131 INTREG_R6_USR = INTREG_R6, 132 INTREG_R7_USR = INTREG_R7, 133 INTREG_R8_USR = INTREG_R8, 134 INTREG_R9_USR = INTREG_R9, 135 INTREG_R10_USR = INTREG_R10, 136 INTREG_R11_USR = INTREG_R11, 137 INTREG_R12_USR = INTREG_R12, 138 INTREG_R13_USR = INTREG_R13, 139 INTREG_SP_USR = INTREG_SP, 140 INTREG_R14_USR = INTREG_R14, 141 INTREG_LR_USR = INTREG_LR, 142 INTREG_R15_USR = INTREG_R15, 143 INTREG_PC_USR = INTREG_PC, 144 145 /* SVC mode */ 146 INTREG_R0_SVC = INTREG_R0, 147 INTREG_R1_SVC = INTREG_R1, 148 INTREG_R2_SVC = INTREG_R2, 149 INTREG_R3_SVC = INTREG_R3, 150 INTREG_R4_SVC = INTREG_R4, 151 INTREG_R5_SVC = INTREG_R5, 152 INTREG_R6_SVC = INTREG_R6, 153 INTREG_R7_SVC = INTREG_R7, 154 INTREG_R8_SVC = INTREG_R8, 155 INTREG_R9_SVC = INTREG_R9, 156 INTREG_R10_SVC = INTREG_R10, 157 INTREG_R11_SVC = INTREG_R11, 158 INTREG_R12_SVC = INTREG_R12, 159 INTREG_PC_SVC = INTREG_PC, 160 INTREG_R15_SVC = INTREG_R15, 161 162 /* MON mode */ 163 INTREG_R0_MON = INTREG_R0, 164 INTREG_R1_MON = INTREG_R1, 165 INTREG_R2_MON = INTREG_R2, 166 INTREG_R3_MON = INTREG_R3, 167 INTREG_R4_MON = INTREG_R4, 168 INTREG_R5_MON = INTREG_R5, 169 INTREG_R6_MON = INTREG_R6, 170 INTREG_R7_MON = INTREG_R7, 171 INTREG_R8_MON = INTREG_R8, 172 INTREG_R9_MON = INTREG_R9, 173 INTREG_R10_MON = INTREG_R10, 174 INTREG_R11_MON = INTREG_R11, 175 INTREG_R12_MON = INTREG_R12, 176 INTREG_PC_MON = INTREG_PC, 177 INTREG_R15_MON = INTREG_R15, 178 179 /* ABT mode */ 180 INTREG_R0_ABT = INTREG_R0, 181 INTREG_R1_ABT = INTREG_R1, 182 INTREG_R2_ABT = INTREG_R2, 183 INTREG_R3_ABT = INTREG_R3, 184 INTREG_R4_ABT = INTREG_R4, 185 INTREG_R5_ABT = INTREG_R5, 186 INTREG_R6_ABT = INTREG_R6, 187 INTREG_R7_ABT = INTREG_R7, 188 INTREG_R8_ABT = INTREG_R8, 189 INTREG_R9_ABT = INTREG_R9, 190 INTREG_R10_ABT = INTREG_R10, 191 INTREG_R11_ABT = INTREG_R11, 192 INTREG_R12_ABT = INTREG_R12, 193 INTREG_PC_ABT = INTREG_PC, 194 INTREG_R15_ABT = INTREG_R15, 195 196 /* UND mode */ 197 INTREG_R0_UND = INTREG_R0, 198 INTREG_R1_UND = INTREG_R1, 199 INTREG_R2_UND = INTREG_R2, 200 INTREG_R3_UND = INTREG_R3, 201 INTREG_R4_UND = INTREG_R4, 202 INTREG_R5_UND = INTREG_R5, 203 INTREG_R6_UND = INTREG_R6, 204 INTREG_R7_UND = INTREG_R7, 205 INTREG_R8_UND = INTREG_R8, 206 INTREG_R9_UND = INTREG_R9, 207 INTREG_R10_UND = INTREG_R10, 208 INTREG_R11_UND = INTREG_R11, 209 INTREG_R12_UND = INTREG_R12, 210 INTREG_PC_UND = INTREG_PC, 211 INTREG_R15_UND = INTREG_R15, 212 213 /* IRQ mode */ 214 INTREG_R0_IRQ = INTREG_R0, 215 INTREG_R1_IRQ = INTREG_R1, 216 INTREG_R2_IRQ = INTREG_R2, 217 INTREG_R3_IRQ = INTREG_R3, 218 INTREG_R4_IRQ = INTREG_R4, 219 INTREG_R5_IRQ = INTREG_R5, 220 INTREG_R6_IRQ = INTREG_R6, 221 INTREG_R7_IRQ = INTREG_R7, 222 INTREG_R8_IRQ = INTREG_R8, 223 INTREG_R9_IRQ = INTREG_R9, 224 INTREG_R10_IRQ = INTREG_R10, 225 INTREG_R11_IRQ = INTREG_R11, 226 INTREG_R12_IRQ = INTREG_R12, 227 INTREG_PC_IRQ = INTREG_PC, 228 INTREG_R15_IRQ = INTREG_R15, 229 230 /* FIQ mode */ 231 INTREG_R0_FIQ = INTREG_R0, 232 INTREG_R1_FIQ = INTREG_R1, 233 INTREG_R2_FIQ = INTREG_R2, 234 INTREG_R3_FIQ = INTREG_R3, 235 INTREG_R4_FIQ = INTREG_R4, 236 INTREG_R5_FIQ = INTREG_R5, 237 INTREG_R6_FIQ = INTREG_R6, 238 INTREG_R7_FIQ = INTREG_R7, 239 INTREG_PC_FIQ = INTREG_PC, 240 INTREG_R15_FIQ = INTREG_R15, 241}; 242 243typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS]; 244 245const IntRegMap IntRegUsrMap = { 246 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR, 247 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR, 248 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR, 249 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR 250}; 251 252static inline IntRegIndex 253INTREG_USR(unsigned index) 254{ 255 assert(index < NUM_ARCH_INTREGS); 256 return IntRegUsrMap[index]; 257} 258 259const IntRegMap IntRegSvcMap = { 260 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC, 261 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC, 262 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC, 263 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC 264}; 265 266static inline IntRegIndex 267INTREG_SVC(unsigned index) 268{ 269 assert(index < NUM_ARCH_INTREGS); 270 return IntRegSvcMap[index]; 271} 272 273const IntRegMap IntRegMonMap = { 274 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON, 275 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON, 276 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON, 277 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON 278}; 279 280static inline IntRegIndex 281INTREG_MON(unsigned index) 282{ 283 assert(index < NUM_ARCH_INTREGS); 284 return IntRegMonMap[index]; 285} 286 287const IntRegMap IntRegAbtMap = { 288 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT, 289 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT, 290 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT, 291 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT 292}; 293 294static inline IntRegIndex 295INTREG_ABT(unsigned index) 296{ 297 assert(index < NUM_ARCH_INTREGS); 298 return IntRegAbtMap[index]; 299} 300 301const IntRegMap IntRegUndMap = { 302 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND, 303 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND, 304 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND, 305 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND 306}; 307 308static inline IntRegIndex 309INTREG_UND(unsigned index) 310{ 311 assert(index < NUM_ARCH_INTREGS); 312 return IntRegUndMap[index]; 313} 314 315const IntRegMap IntRegIrqMap = { 316 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ, 317 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ, 318 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ, 319 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ 320}; 321 322static inline IntRegIndex 323INTREG_IRQ(unsigned index) 324{ 325 assert(index < NUM_ARCH_INTREGS); 326 return IntRegIrqMap[index]; 327} 328 329const IntRegMap IntRegFiqMap = { 330 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ, 331 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ, 332 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ, 333 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ 334}; 335 336static inline IntRegIndex 337INTREG_FIQ(unsigned index) 338{ 339 assert(index < NUM_ARCH_INTREGS); 340 return IntRegFiqMap[index]; 341} 342 343static const unsigned intRegsPerMode = NUM_INTREGS; 344 345static inline int 346intRegInMode(OperatingMode mode, int reg) 347{ 348 assert(reg < NUM_ARCH_INTREGS); 349 return mode * intRegsPerMode + reg; 350} 351 352} 353 354#endif 355