interrupts.hh revision 3827
18968Snilay@cs.wisc.edu/* 28968Snilay@cs.wisc.edu * Copyright (c) 2006 The Regents of The University of Michigan 38968Snilay@cs.wisc.edu * All rights reserved. 48968Snilay@cs.wisc.edu * 58968Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 68968Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 78968Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 88968Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 98968Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 108968Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 118968Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 128968Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 138968Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 148968Snilay@cs.wisc.edu * this software without specific prior written permission. 158968Snilay@cs.wisc.edu * 168968Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178968Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188968Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198968Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208968Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218968Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228968Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238968Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248968Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258968Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268968Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278968Snilay@cs.wisc.edu * 288968Snilay@cs.wisc.edu * Authors: Gabe Black 298968Snilay@cs.wisc.edu */ 308968Snilay@cs.wisc.edu 318968Snilay@cs.wisc.edu#ifndef __ARCH_SPARC_INTERRUPT_HH__ 328968Snilay@cs.wisc.edu#define __ARCH_SPARC_INTERRUPT_HH__ 338968Snilay@cs.wisc.edu 348968Snilay@cs.wisc.edu#include "arch/sparc/faults.hh" 358968Snilay@cs.wisc.edu#include "cpu/thread_context.hh" 369123Sandreas.hansson@arm.com 378968Snilay@cs.wisc.edu 388968Snilay@cs.wisc.edunamespace SparcISA 398968Snilay@cs.wisc.edu{ 408968Snilay@cs.wisc.edu class Interrupts 418968Snilay@cs.wisc.edu { 428968Snilay@cs.wisc.edu protected: 438968Snilay@cs.wisc.edu 448968Snilay@cs.wisc.edu 458968Snilay@cs.wisc.edu public: 468968Snilay@cs.wisc.edu Interrupts() 478968Snilay@cs.wisc.edu { 488968Snilay@cs.wisc.edu 498968Snilay@cs.wisc.edu } 508968Snilay@cs.wisc.edu void post(int int_num, int index) 518968Snilay@cs.wisc.edu { 528968Snilay@cs.wisc.edu 538968Snilay@cs.wisc.edu } 548968Snilay@cs.wisc.edu 558968Snilay@cs.wisc.edu void clear(int int_num, int index) 568968Snilay@cs.wisc.edu { 578968Snilay@cs.wisc.edu 589826Sandreas.hansson@arm.com } 599802Snilay@cs.wisc.edu 609827Sakash.bagdia@arm.com void clear_all() 619827Sakash.bagdia@arm.com { 629793Sakash.bagdia@arm.com 638968Snilay@cs.wisc.edu } 649827Sakash.bagdia@arm.com 659827Sakash.bagdia@arm.com bool check_interrupts(ThreadContext * tc) const 669827Sakash.bagdia@arm.com { 679827Sakash.bagdia@arm.com // so far only handle softint interrupts 689802Snilay@cs.wisc.edu int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 699802Snilay@cs.wisc.edu if (int_level) 709793Sakash.bagdia@arm.com return true; 7110519Snilay@cs.wisc.edu else 728968Snilay@cs.wisc.edu return false; 739793Sakash.bagdia@arm.com } 749827Sakash.bagdia@arm.com 759827Sakash.bagdia@arm.com Fault getInterrupt(ThreadContext * tc) 769793Sakash.bagdia@arm.com { 7710519Snilay@cs.wisc.edu // conditioning the softint interrups 7810519Snilay@cs.wisc.edu if (tc->readMiscReg(MISCREG_HPSTATE) & hpriv) { 7910519Snilay@cs.wisc.edu // if running in privileged mode, then pend the interrupt 8010519Snilay@cs.wisc.edu return NoFault; 818968Snilay@cs.wisc.edu } else { 828968Snilay@cs.wisc.edu int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 838968Snilay@cs.wisc.edu if ((int_level <= tc->readMiscReg(MISCREG_PIL)) || 848968Snilay@cs.wisc.edu !(tc->readMiscReg(MISCREG_PSTATE) & ie)) { 8510120Snilay@cs.wisc.edu // if PIL or no interrupt enabled, then pend the interrupt 8610120Snilay@cs.wisc.edu return NoFault; 8710120Snilay@cs.wisc.edu } else { 8810120Snilay@cs.wisc.edu return new InterruptLevelN(int_level); 8910519Snilay@cs.wisc.edu } 9010120Snilay@cs.wisc.edu } 9110120Snilay@cs.wisc.edu } 9210120Snilay@cs.wisc.edu 938968Snilay@cs.wisc.edu void updateIntrInfo(ThreadContext * tc) 9410519Snilay@cs.wisc.edu { 959826Sandreas.hansson@arm.com 969826Sandreas.hansson@arm.com } 978968Snilay@cs.wisc.edu 988968Snilay@cs.wisc.edu void serialize(std::ostream &os) 99 { 100 } 101 102 void unserialize(Checkpoint *cp, const std::string §ion) 103 { 104 } 105 }; 106} 107 108#endif // __ARCH_SPARC_INTERRUPT_HH__ 109