interrupts.hh revision 3827
18968Snilay@cs.wisc.edu/*
28968Snilay@cs.wisc.edu * Copyright (c) 2006 The Regents of The University of Michigan
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88968Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer;
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148968Snilay@cs.wisc.edu * this software without specific prior written permission.
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278968Snilay@cs.wisc.edu *
288968Snilay@cs.wisc.edu * Authors: Gabe Black
298968Snilay@cs.wisc.edu */
308968Snilay@cs.wisc.edu
318968Snilay@cs.wisc.edu#ifndef __ARCH_SPARC_INTERRUPT_HH__
328968Snilay@cs.wisc.edu#define __ARCH_SPARC_INTERRUPT_HH__
338968Snilay@cs.wisc.edu
348968Snilay@cs.wisc.edu#include "arch/sparc/faults.hh"
358968Snilay@cs.wisc.edu#include "cpu/thread_context.hh"
369123Sandreas.hansson@arm.com
378968Snilay@cs.wisc.edu
388968Snilay@cs.wisc.edunamespace SparcISA
398968Snilay@cs.wisc.edu{
408968Snilay@cs.wisc.edu    class Interrupts
418968Snilay@cs.wisc.edu    {
428968Snilay@cs.wisc.edu      protected:
438968Snilay@cs.wisc.edu
448968Snilay@cs.wisc.edu
458968Snilay@cs.wisc.edu      public:
468968Snilay@cs.wisc.edu        Interrupts()
478968Snilay@cs.wisc.edu        {
488968Snilay@cs.wisc.edu
498968Snilay@cs.wisc.edu        }
508968Snilay@cs.wisc.edu        void post(int int_num, int index)
518968Snilay@cs.wisc.edu        {
528968Snilay@cs.wisc.edu
538968Snilay@cs.wisc.edu        }
548968Snilay@cs.wisc.edu
558968Snilay@cs.wisc.edu        void clear(int int_num, int index)
568968Snilay@cs.wisc.edu        {
578968Snilay@cs.wisc.edu
589826Sandreas.hansson@arm.com        }
599802Snilay@cs.wisc.edu
609827Sakash.bagdia@arm.com        void clear_all()
619827Sakash.bagdia@arm.com        {
629793Sakash.bagdia@arm.com
638968Snilay@cs.wisc.edu        }
649827Sakash.bagdia@arm.com
659827Sakash.bagdia@arm.com        bool check_interrupts(ThreadContext * tc) const
669827Sakash.bagdia@arm.com        {
679827Sakash.bagdia@arm.com            // so far only handle softint interrupts
689802Snilay@cs.wisc.edu            int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
699802Snilay@cs.wisc.edu            if (int_level)
709793Sakash.bagdia@arm.com                return true;
7110519Snilay@cs.wisc.edu            else
728968Snilay@cs.wisc.edu                return false;
739793Sakash.bagdia@arm.com        }
749827Sakash.bagdia@arm.com
759827Sakash.bagdia@arm.com        Fault getInterrupt(ThreadContext * tc)
769793Sakash.bagdia@arm.com        {
7710519Snilay@cs.wisc.edu            // conditioning the softint interrups
7810519Snilay@cs.wisc.edu            if (tc->readMiscReg(MISCREG_HPSTATE) & hpriv) {
7910519Snilay@cs.wisc.edu                // if running in privileged mode, then pend the interrupt
8010519Snilay@cs.wisc.edu                return NoFault;
818968Snilay@cs.wisc.edu            } else {
828968Snilay@cs.wisc.edu                int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
838968Snilay@cs.wisc.edu                if ((int_level <= tc->readMiscReg(MISCREG_PIL)) ||
848968Snilay@cs.wisc.edu                    !(tc->readMiscReg(MISCREG_PSTATE) & ie)) {
8510120Snilay@cs.wisc.edu                    // if PIL or no interrupt enabled, then pend the interrupt
8610120Snilay@cs.wisc.edu                    return NoFault;
8710120Snilay@cs.wisc.edu                } else {
8810120Snilay@cs.wisc.edu                    return new InterruptLevelN(int_level);
8910519Snilay@cs.wisc.edu                }
9010120Snilay@cs.wisc.edu            }
9110120Snilay@cs.wisc.edu        }
9210120Snilay@cs.wisc.edu
938968Snilay@cs.wisc.edu        void updateIntrInfo(ThreadContext * tc)
9410519Snilay@cs.wisc.edu        {
959826Sandreas.hansson@arm.com
969826Sandreas.hansson@arm.com        }
978968Snilay@cs.wisc.edu
988968Snilay@cs.wisc.edu        void serialize(std::ostream &os)
99        {
100        }
101
102        void unserialize(Checkpoint *cp, const std::string &section)
103        {
104        }
105    };
106}
107
108#endif // __ARCH_SPARC_INTERRUPT_HH__
109