interrupts.hh revision 7847
13537SN/A/* 27400SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37400SAli.Saidi@ARM.com * All rights reserved 47400SAli.Saidi@ARM.com * 57400SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67400SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77400SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87400SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97400SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107400SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117400SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127400SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137400SAli.Saidi@ARM.com * 143537SN/A * Copyright (c) 2006 The Regents of The University of Michigan 153537SN/A * All rights reserved. 163537SN/A * 173537SN/A * Redistribution and use in source and binary forms, with or without 183537SN/A * modification, are permitted provided that the following conditions are 193537SN/A * met: redistributions of source code must retain the above copyright 203537SN/A * notice, this list of conditions and the following disclaimer; 213537SN/A * redistributions in binary form must reproduce the above copyright 223537SN/A * notice, this list of conditions and the following disclaimer in the 233537SN/A * documentation and/or other materials provided with the distribution; 243537SN/A * neither the name of the copyright holders nor the names of its 253537SN/A * contributors may be used to endorse or promote products derived from 263537SN/A * this software without specific prior written permission. 273537SN/A * 283537SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293537SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303537SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313537SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323537SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333537SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343537SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353537SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363537SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373537SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383537SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394103SN/A * 404103SN/A * Authors: Ali Saidi 413537SN/A */ 423537SN/A 436757SAli.Saidi@ARM.com#ifndef __ARCH_ARM_INTERRUPT_HH__ 446757SAli.Saidi@ARM.com#define __ARCH_ARM_INTERRUPT_HH__ 453537SN/A 466757SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 476757SAli.Saidi@ARM.com#include "arch/arm/isa_traits.hh" 487400SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 496757SAli.Saidi@ARM.com#include "arch/arm/registers.hh" 503827SN/A#include "cpu/thread_context.hh" 516757SAli.Saidi@ARM.com#include "params/ArmInterrupts.hh" 525647SN/A#include "sim/sim_object.hh" 533827SN/A 546757SAli.Saidi@ARM.comnamespace ArmISA 553537SN/A{ 563894SN/A 575647SN/Aclass Interrupts : public SimObject 584009SN/A{ 595810SN/A private: 605810SN/A BaseCPU * cpu; 614009SN/A 627400SAli.Saidi@ARM.com bool interrupts[NumInterruptTypes]; 634103SN/A uint64_t intStatus; 644009SN/A 654009SN/A public: 665810SN/A 675810SN/A void 685810SN/A setCPU(BaseCPU * _cpu) 695810SN/A { 705810SN/A cpu = _cpu; 715810SN/A } 725810SN/A 736757SAli.Saidi@ARM.com typedef ArmInterruptsParams Params; 745647SN/A 755647SN/A const Params * 765647SN/A params() const 775647SN/A { 785647SN/A return dynamic_cast<const Params *>(_params); 795647SN/A } 805647SN/A 815810SN/A Interrupts(Params * p) : SimObject(p), cpu(NULL) 824009SN/A { 835704SN/A clearAll(); 844009SN/A } 854009SN/A 864009SN/A 875704SN/A void 885704SN/A post(int int_num, int index) 893537SN/A { 907400SAli.Saidi@ARM.com DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 917400SAli.Saidi@ARM.com 927400SAli.Saidi@ARM.com if (int_num < 0 || int_num >= NumInterruptTypes) 937400SAli.Saidi@ARM.com panic("int_num out of bounds\n"); 947400SAli.Saidi@ARM.com 957400SAli.Saidi@ARM.com if (index != 0) 967400SAli.Saidi@ARM.com panic("No support for other interrupt indexes\n"); 977400SAli.Saidi@ARM.com 987400SAli.Saidi@ARM.com interrupts[int_num] = true; 997400SAli.Saidi@ARM.com intStatus |= ULL(1) << int_num; 1004009SN/A } 1013894SN/A 1025704SN/A void 1035704SN/A clear(int int_num, int index) 1044009SN/A { 1057847Sminkyu.jeong@arm.com DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 1067400SAli.Saidi@ARM.com 1077400SAli.Saidi@ARM.com if (int_num < 0 || int_num >= NumInterruptTypes) 1087400SAli.Saidi@ARM.com panic("int_num out of bounds\n"); 1097400SAli.Saidi@ARM.com 1107400SAli.Saidi@ARM.com if (index != 0) 1117400SAli.Saidi@ARM.com panic("No support for other interrupt indexes\n"); 1127400SAli.Saidi@ARM.com 1137400SAli.Saidi@ARM.com interrupts[int_num] = false; 1147400SAli.Saidi@ARM.com intStatus &= ~(ULL(1) << int_num); 1154009SN/A } 1163827SN/A 1175704SN/A void 1185704SN/A clearAll() 1194009SN/A { 1207400SAli.Saidi@ARM.com DPRINTF(Interrupt, "Interrupts all cleared\n"); 1214103SN/A intStatus = 0; 1227400SAli.Saidi@ARM.com memset(interrupts, 0, sizeof(interrupts)); 1234009SN/A } 1243537SN/A 1255704SN/A bool 1265704SN/A checkInterrupts(ThreadContext *tc) const 1274009SN/A { 1287400SAli.Saidi@ARM.com if (!intStatus) 1297400SAli.Saidi@ARM.com return false; 1307400SAli.Saidi@ARM.com 1317400SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1327400SAli.Saidi@ARM.com 1337400SAli.Saidi@ARM.com return ((interrupts[INT_IRQ] && !cpsr.i) || 1347400SAli.Saidi@ARM.com (interrupts[INT_FIQ] && !cpsr.f) || 1357400SAli.Saidi@ARM.com (interrupts[INT_ABT] && !cpsr.a) || 1367400SAli.Saidi@ARM.com (interrupts[INT_RST])); 1374009SN/A } 1383537SN/A 1395704SN/A Fault 1405704SN/A getInterrupt(ThreadContext *tc) 1414009SN/A { 1427400SAli.Saidi@ARM.com if (!intStatus) 1437400SAli.Saidi@ARM.com return NoFault; 1447400SAli.Saidi@ARM.com 1457400SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1467400SAli.Saidi@ARM.com 1477400SAli.Saidi@ARM.com if (interrupts[INT_IRQ] && !cpsr.i) 1487400SAli.Saidi@ARM.com return new Interrupt; 1497400SAli.Saidi@ARM.com if (interrupts[INT_FIQ] && !cpsr.f) 1507400SAli.Saidi@ARM.com return new FastInterrupt; 1517400SAli.Saidi@ARM.com if (interrupts[INT_ABT] && !cpsr.a) 1527400SAli.Saidi@ARM.com return new DataAbort(0, false, 0, 1537400SAli.Saidi@ARM.com ArmFault::AsynchronousExternalAbort); 1547400SAli.Saidi@ARM.com if (interrupts[INT_RST]) 1557400SAli.Saidi@ARM.com return new Reset; 1567400SAli.Saidi@ARM.com 1577400SAli.Saidi@ARM.com panic("intStatus and interrupts not in sync\n"); 1584009SN/A } 1593537SN/A 1605704SN/A void 1615704SN/A updateIntrInfo(ThreadContext *tc) 1624009SN/A { 1637400SAli.Saidi@ARM.com ; // nothing to do 1644009SN/A } 1653654SN/A 1665704SN/A void 1675704SN/A serialize(std::ostream &os) 1684009SN/A { 1697400SAli.Saidi@ARM.com SERIALIZE_ARRAY(interrupts, NumInterruptTypes); 1707400SAli.Saidi@ARM.com SERIALIZE_SCALAR(intStatus); 1714009SN/A } 1723537SN/A 1735704SN/A void 1745704SN/A unserialize(Checkpoint *cp, const std::string §ion) 1754009SN/A { 1767400SAli.Saidi@ARM.com UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes); 1777400SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(intStatus); 1784009SN/A } 1794009SN/A}; 1806757SAli.Saidi@ARM.com} // namespace ARM_ISA 1813537SN/A 1826757SAli.Saidi@ARM.com#endif // __ARCH_ARM_INTERRUPT_HH__ 183