interrupts.hh revision 5704 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Lisa Hsu
30 */
31
32#ifndef __ARCH_SPARC_INTERRUPT_HH__
33#define __ARCH_SPARC_INTERRUPT_HH__
34
35#include "arch/sparc/faults.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "cpu/thread_context.hh"
38#include "params/SparcInterrupts.hh"
39#include "sim/sim_object.hh"
40
41namespace SparcISA
42{
43
44class Interrupts : public SimObject
45{
46
47  private:
48    uint64_t interrupts[NumInterruptTypes];
49    uint64_t intStatus;
50
51  public:
52    typedef SparcInterruptsParams Params;
53
54    const Params *
55    params() const
56    {
57        return dynamic_cast<const Params *>(_params);
58    }
59
60    Interrupts(Params * p) : SimObject(p)
61    {
62        clearAll();
63    }
64
65    int
66    InterruptLevel(uint64_t softint)
67    {
68        if (softint & 0x10000 || softint & 0x1)
69            return 14;
70
71        int level = 15;
72        while (level > 0 && !(1 << level & softint))
73            level--;
74        if (1 << level & softint)
75            return level;
76        return 0;
77    }
78
79    void
80    post(int int_num, int index)
81    {
82        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
83        assert(int_num >= 0 && int_num < NumInterruptTypes);
84        assert(index >= 0 && index < 64);
85
86        interrupts[int_num] |= ULL(1) << index;
87        intStatus |= ULL(1) << int_num;
88    }
89
90    void
91    clear(int int_num, int index)
92    {
93        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
94        assert(int_num >= 0 && int_num < NumInterruptTypes);
95        assert(index >= 0 && index < 64);
96
97        interrupts[int_num] &= ~(ULL(1) << index);
98        if (!interrupts[int_num])
99            intStatus &= ~(ULL(1) << int_num);
100    }
101
102    void
103    clearAll()
104    {
105        for (int i = 0; i < NumInterruptTypes; ++i) {
106            interrupts[i] = 0;
107        }
108        intStatus = 0;
109    }
110
111    bool
112    checkInterrupts(ThreadContext *tc) const
113    {
114        return intStatus;
115    }
116
117    Fault
118    getInterrupt(ThreadContext *tc)
119    {
120        int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
121        int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
122        bool ie = pstate & PSTATE::ie;
123
124        // THESE ARE IN ORDER OF PRIORITY
125        // since there are early returns, and the highest
126        // priority interrupts should get serviced,
127        // it is v. important that new interrupts are inserted
128        // in the right order of processing
129        if (hpstate & HPSTATE::hpriv) {
130            if (ie) {
131                if (interrupts[IT_HINTP]) {
132                    // This will be cleaned by a HINTP write
133                    return new HstickMatch;
134                }
135                if (interrupts[IT_INT_VEC]) {
136                    // this will be cleared by an ASI read (or write)
137                    return new InterruptVector;
138                }
139            }
140        } else {
141            if (interrupts[IT_TRAP_LEVEL_ZERO]) {
142                    // this is cleared by deasserting HPSTATE::tlz
143                    return new TrapLevelZero;
144            }
145            // HStick matches always happen in priv mode (ie doesn't matter)
146            if (interrupts[IT_HINTP]) {
147                return new HstickMatch;
148            }
149            if (interrupts[IT_INT_VEC]) {
150                // this will be cleared by an ASI read (or write)
151                return new InterruptVector;
152            }
153            if (ie) {
154                if (interrupts[IT_CPU_MONDO]) {
155                    return new CpuMondo;
156                }
157                if (interrupts[IT_DEV_MONDO]) {
158                    return new DevMondo;
159                }
160                if (interrupts[IT_SOFT_INT]) {
161                    int level = InterruptLevel(interrupts[IT_SOFT_INT]);
162                    return new InterruptLevelN(level);
163                }
164
165                if (interrupts[IT_RES_ERROR]) {
166                    return new ResumableError;
167                }
168            } // !hpriv && ie
169        }  // !hpriv
170        return NoFault;
171    }
172
173    void
174    updateIntrInfo(ThreadContext *tc)
175    {
176
177    }
178
179    uint64_t
180    get_vec(int int_num)
181    {
182        assert(int_num >= 0 && int_num < NumInterruptTypes);
183        return interrupts[int_num];
184    }
185
186    void
187    serialize(std::ostream &os)
188    {
189        SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
190        SERIALIZE_SCALAR(intStatus);
191    }
192
193    void
194    unserialize(Checkpoint *cp, const std::string &section)
195    {
196        UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
197        UNSERIALIZE_SCALAR(intStatus);
198    }
199};
200} // namespace SPARC_ISA
201
202#endif // __ARCH_SPARC_INTERRUPT_HH__
203