interrupts.cc revision 11581:d6cfd0be73b2
14019Sstever@eecs.umich.edu/* 23187Srdreslin@umich.edu * Copyright (c) 2009, 2012-2013, 2016 ARM Limited 33187Srdreslin@umich.edu * All rights reserved. 43187Srdreslin@umich.edu * 53187Srdreslin@umich.edu * The license below extends only to copyright in the software and shall 63187Srdreslin@umich.edu * not be construed as granting a license to any other intellectual 73187Srdreslin@umich.edu * property including but not limited to intellectual property relating 83187Srdreslin@umich.edu * to a hardware implementation of the functionality of the software 93187Srdreslin@umich.edu * licensed hereunder. You may use the software subject to the license 103187Srdreslin@umich.edu * terms below provided that you ensure that this notice is replicated 113187Srdreslin@umich.edu * unmodified and in its entirety in all distributions of the software, 123187Srdreslin@umich.edu * modified or unmodified, in source code or in binary form. 133187Srdreslin@umich.edu * 143187Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 153187Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 163187Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 173187Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 183187Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 193187Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 203187Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 213187Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 223187Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 233187Srdreslin@umich.edu * this software without specific prior written permission. 243187Srdreslin@umich.edu * 253187Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 263187Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 273187Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 283187Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 293187Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 303187Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 313187Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 323187Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 333187Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 343187Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353187Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363187Srdreslin@umich.edu * 374444Ssaidi@eecs.umich.edu * Authors: Ali Saidi 383187Srdreslin@umich.edu */ 393208Srdreslin@umich.edu 403187Srdreslin@umich.edu#include "arch/arm/interrupts.hh" 413187Srdreslin@umich.edu#include "arch/arm/system.hh" 423187Srdreslin@umich.edu 433187Srdreslin@umich.eduArmISA::Interrupts * 443187Srdreslin@umich.eduArmInterruptsParams::create() 453187Srdreslin@umich.edu{ 463187Srdreslin@umich.edu return new ArmISA::Interrupts(this); 473187Srdreslin@umich.edu} 483187Srdreslin@umich.edu 494444Ssaidi@eecs.umich.edubool 503187Srdreslin@umich.eduArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const 513187Srdreslin@umich.edu{ 523187Srdreslin@umich.edu // Table G1-17~19 of ARM V8 ARM 533187Srdreslin@umich.edu InterruptMask mask; 543196Srdreslin@umich.edu bool highest_el_is_64 = ArmSystem::highestELIs64(tc); 553196Srdreslin@umich.edu 564019Sstever@eecs.umich.edu CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 573187Srdreslin@umich.edu SCR scr; 583187Srdreslin@umich.edu HCR hcr; 593187Srdreslin@umich.edu hcr = tc->readMiscReg(MISCREG_HCR); 604467Sstever@eecs.umich.edu ExceptionLevel el = (ExceptionLevel) ((uint32_t) cpsr.el); 614467Sstever@eecs.umich.edu bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit; 623187Srdreslin@umich.edu 633187Srdreslin@umich.edu if (!highest_el_is_64) 643257Srdreslin@umich.edu scr = tc->readMiscReg(MISCREG_SCR); 653208Srdreslin@umich.edu else 663187Srdreslin@umich.edu scr = tc->readMiscReg(MISCREG_SCR_EL3); 673187Srdreslin@umich.edu 683187Srdreslin@umich.edu bool is_secure = inSecureState(tc); 693187Srdreslin@umich.edu 703187Srdreslin@umich.edu switch(int_type) { 713187Srdreslin@umich.edu case INT_FIQ: 723187Srdreslin@umich.edu cpsr_mask_bit = cpsr.f; 733187Srdreslin@umich.edu scr_routing_bit = scr.fiq; 743187Srdreslin@umich.edu scr_fwaw_bit = scr.fw; 753187Srdreslin@umich.edu hcr_mask_override_bit = hcr.fmo; 764467Sstever@eecs.umich.edu break; 773187Srdreslin@umich.edu case INT_IRQ: 783187Srdreslin@umich.edu cpsr_mask_bit = cpsr.i; 793187Srdreslin@umich.edu scr_routing_bit = scr.irq; 803187Srdreslin@umich.edu scr_fwaw_bit = 1; 813187Srdreslin@umich.edu hcr_mask_override_bit = hcr.imo; 823187Srdreslin@umich.edu break; 833187Srdreslin@umich.edu case INT_ABT: 843187Srdreslin@umich.edu cpsr_mask_bit = cpsr.a; 853187Srdreslin@umich.edu scr_routing_bit = scr.ea; 863187Srdreslin@umich.edu scr_fwaw_bit = scr.aw; 873187Srdreslin@umich.edu hcr_mask_override_bit = hcr.amo; 883341Srdreslin@umich.edu break; 893341Srdreslin@umich.edu default: 903257Srdreslin@umich.edu panic("Unhandled interrupt type!"); 91 } 92 93 if (hcr.tge) 94 hcr_mask_override_bit = 1; 95 96 if (!highest_el_is_64) { 97 // AArch32 98 if (!scr_routing_bit) { 99 // SCR IRQ == 0 100 if (!hcr_mask_override_bit) 101 mask = INT_MASK_M; 102 else { 103 if (!is_secure && (el == EL0 || el == EL1)) 104 mask = INT_MASK_T; 105 else 106 mask = INT_MASK_M; 107 } 108 } else { 109 // SCR IRQ == 1 110 if ((!is_secure) && 111 (hcr_mask_override_bit || 112 (!scr_fwaw_bit && !hcr_mask_override_bit))) 113 mask = INT_MASK_T; 114 else 115 mask = INT_MASK_M; 116 } 117 } else { 118 // AArch64 119 if (!scr_routing_bit) { 120 // SCR IRQ == 0 121 if (!scr.rw) { 122 // SCR RW == 0 123 if (!hcr_mask_override_bit) { 124 if (el == EL3) 125 mask = INT_MASK_P; 126 else 127 mask = INT_MASK_M; 128 } else { 129 if (el == EL3) 130 mask = INT_MASK_T; 131 else if (is_secure || el == EL2) 132 mask = INT_MASK_M; 133 else 134 mask = INT_MASK_T; 135 } 136 } else { 137 // SCR RW == 1 138 if (!hcr_mask_override_bit) { 139 if (el == EL3 || el == EL2) 140 mask = INT_MASK_P; 141 else 142 mask = INT_MASK_M; 143 } else { 144 if (el == EL3) 145 mask = INT_MASK_P; 146 else if (is_secure || el == EL2) 147 mask = INT_MASK_M; 148 else 149 mask = INT_MASK_T; 150 } 151 } 152 } else { 153 // SCR IRQ == 1 154 if (el == EL3) 155 mask = INT_MASK_M; 156 else 157 mask = INT_MASK_T; 158 } 159 } 160 161 return ((mask == INT_MASK_T) || 162 ((mask == INT_MASK_M) && !cpsr_mask_bit)) && 163 (mask != INT_MASK_P); 164} 165 166