static_inst.hh revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "arch/arm/faults.hh"
46#include "arch/arm/utility.hh"
47#include "base/trace.hh"
48#include "cpu/static_inst.hh"
49
50namespace ArmISA
51{
52
53class ArmStaticInst : public StaticInst
54{
55  protected:
56    int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
57                         uint32_t type, uint32_t cfval) const;
58    int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
59                        uint32_t type, uint32_t cfval) const;
60
61    bool shift_carry_imm(uint32_t base, uint32_t shamt,
62                         uint32_t type, uint32_t cfval) const;
63    bool shift_carry_rs(uint32_t base, uint32_t shamt,
64                        uint32_t type, uint32_t cfval) const;
65
66    template<int width>
67    static inline bool
68    saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
69    {
70        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
71        if (bits(midRes, width) != bits(midRes, width - 1)) {
72            if (midRes > 0)
73                res = (LL(1) << (width - 1)) - 1;
74            else
75                res = -(LL(1) << (width - 1));
76            return true;
77        } else {
78            res = midRes;
79            return false;
80        }
81    }
82
83    static inline bool
84    satInt(int32_t &res, int64_t op, int width)
85    {
86        width--;
87        if (op >= (LL(1) << width)) {
88            res = (LL(1) << width) - 1;
89            return true;
90        } else if (op < -(LL(1) << width)) {
91            res = -(LL(1) << width);
92            return true;
93        } else {
94            res = op;
95            return false;
96        }
97    }
98
99    template<int width>
100    static inline bool
101    uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
102    {
103        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
104        if (midRes >= (LL(1) << width)) {
105            res = (LL(1) << width) - 1;
106            return true;
107        } else if (midRes < 0) {
108            res = 0;
109            return true;
110        } else {
111            res = midRes;
112            return false;
113        }
114    }
115
116    static inline bool
117    uSatInt(int32_t &res, int64_t op, int width)
118    {
119        if (op >= (LL(1) << width)) {
120            res = (LL(1) << width) - 1;
121            return true;
122        } else if (op < 0) {
123            res = 0;
124            return true;
125        } else {
126            res = op;
127            return false;
128        }
129    }
130
131    // Constructor
132    ArmStaticInst(const char *mnem, ExtMachInst _machInst,
133                  OpClass __opClass)
134        : StaticInst(mnem, _machInst, __opClass)
135    {
136    }
137
138    /// Print a register name for disassembly given the unique
139    /// dependence tag number (FP or int).
140    void printReg(std::ostream &os, int reg) const;
141    void printMnemonic(std::ostream &os,
142                       const std::string &suffix = "",
143                       bool withPred = true) const;
144    void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
145                        const std::string &prefix, const Addr addr,
146                        const std::string &suffix) const;
147    void printShiftOperand(std::ostream &os, IntRegIndex rm,
148                           bool immShift, uint32_t shiftAmt,
149                           IntRegIndex rs, ArmShiftType type) const;
150
151
152    void printDataInst(std::ostream &os, bool withImm) const;
153    void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
154                       IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
155                       IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
156                       uint32_t imm) const;
157
158    void
159    advancePC(PCState &pcState) const
160    {
161        pcState.advance();
162    }
163
164    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
165
166    static inline uint32_t
167    cpsrWriteByInstr(CPSR cpsr, uint32_t val,
168            uint8_t byteMask, bool affectState, bool nmfi)
169    {
170        bool privileged = (cpsr.mode != MODE_USER);
171
172        uint32_t bitMask = 0;
173
174        if (bits(byteMask, 3)) {
175            unsigned lowIdx = affectState ? 24 : 27;
176            bitMask = bitMask | mask(31, lowIdx);
177        }
178        if (bits(byteMask, 2)) {
179            bitMask = bitMask | mask(19, 16);
180        }
181        if (bits(byteMask, 1)) {
182            unsigned highIdx = affectState ? 15 : 9;
183            unsigned lowIdx = privileged ? 8 : 9;
184            bitMask = bitMask | mask(highIdx, lowIdx);
185        }
186        if (bits(byteMask, 0)) {
187            if (privileged) {
188                bitMask = bitMask | mask(7, 6);
189                if (!badMode((OperatingMode)(val & mask(5)))) {
190                    bitMask = bitMask | mask(5);
191                } else {
192                    warn_once("Ignoring write of bad mode to CPSR.\n");
193                }
194            }
195            if (affectState)
196                bitMask = bitMask | (1 << 5);
197        }
198
199        bool cpsr_f = cpsr.f;
200        uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
201        if (nmfi && !cpsr_f)
202            new_cpsr &= ~(1 << 6);
203        return new_cpsr;
204    }
205
206    static inline uint32_t
207    spsrWriteByInstr(uint32_t spsr, uint32_t val,
208            uint8_t byteMask, bool affectState)
209    {
210        uint32_t bitMask = 0;
211
212        if (bits(byteMask, 3))
213            bitMask = bitMask | mask(31, 24);
214        if (bits(byteMask, 2))
215            bitMask = bitMask | mask(19, 16);
216        if (bits(byteMask, 1))
217            bitMask = bitMask | mask(15, 8);
218        if (bits(byteMask, 0))
219            bitMask = bitMask | mask(7, 0);
220
221        return ((spsr & ~bitMask) | (val & bitMask));
222    }
223
224    template<class XC>
225    static inline Addr
226    readPC(XC *xc)
227    {
228        return xc->pcState().instPC();
229    }
230
231    template<class XC>
232    static inline void
233    setNextPC(XC *xc, Addr val)
234    {
235        PCState pc = xc->pcState();
236        pc.instNPC(val);
237        xc->pcState(pc);
238    }
239
240    template<class T>
241    static inline T
242    cSwap(T val, bool big)
243    {
244        if (big) {
245            return gtobe(val);
246        } else {
247            return gtole(val);
248        }
249    }
250
251    template<class T, class E>
252    static inline T
253    cSwap(T val, bool big)
254    {
255        const unsigned count = sizeof(T) / sizeof(E);
256        union {
257            T tVal;
258            E eVals[count];
259        } conv;
260        conv.tVal = htog(val);
261        if (big) {
262            for (unsigned i = 0; i < count; i++) {
263                conv.eVals[i] = gtobe(conv.eVals[i]);
264            }
265        } else {
266            for (unsigned i = 0; i < count; i++) {
267                conv.eVals[i] = gtole(conv.eVals[i]);
268            }
269        }
270        return gtoh(conv.tVal);
271    }
272
273    // Perform an interworking branch.
274    template<class XC>
275    static inline void
276    setIWNextPC(XC *xc, Addr val)
277    {
278        PCState pc = xc->pcState();
279        pc.instIWNPC(val);
280        xc->pcState(pc);
281    }
282
283    // Perform an interworking branch in ARM mode, a regular branch
284    // otherwise.
285    template<class XC>
286    static inline void
287    setAIWNextPC(XC *xc, Addr val)
288    {
289        PCState pc = xc->pcState();
290        pc.instAIWNPC(val);
291        xc->pcState(pc);
292    }
293
294    inline Fault
295    disabledFault() const
296    {
297#if FULL_SYSTEM
298            return new UndefinedInstruction();
299#else
300            return new UndefinedInstruction(machInst, false, mnemonic, true);
301#endif
302    }
303};
304}
305
306#endif //__ARCH_ARM_INSTS_STATICINST_HH__
307