static_inst.hh revision 6262:43950710afdc
1/* Copyright (c) 2007-2008 The Florida State University 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution; 11 * neither the name of the copyright holders nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Authors: Stephen Hines 28 */ 29#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 30#define __ARCH_ARM_INSTS_STATICINST_HH__ 31 32#include "base/trace.hh" 33#include "cpu/static_inst.hh" 34 35namespace ArmISA 36{ 37class ArmStaticInst : public StaticInst 38{ 39 protected: 40 int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 41 uint32_t type, uint32_t cfval) const; 42 int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 43 uint32_t type, uint32_t cfval) const; 44 45 bool shift_carry_imm(uint32_t base, uint32_t shamt, 46 uint32_t type, uint32_t cfval) const; 47 bool shift_carry_rs(uint32_t base, uint32_t shamt, 48 uint32_t type, uint32_t cfval) const; 49 50 bool arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const; 51 bool arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const; 52 53 bool arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const; 54 bool arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const; 55 56 // Constructor 57 ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) 58 : StaticInst(mnem, _machInst, __opClass) 59 { 60 } 61 62 /// Print a register name for disassembly given the unique 63 /// dependence tag number (FP or int). 64 void printReg(std::ostream &os, int reg) const; 65 void printMnemonic(std::ostream &os, 66 const std::string &suffix = "", 67 bool withPred = true) const; 68 69 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 70}; 71} 72 73#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 74