static_inst.hh revision 12109:f29e9c5418aa
1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 43#define __ARCH_ARM_INSTS_STATICINST_HH__ 44 45#include <memory> 46 47#include "arch/arm/faults.hh" 48#include "arch/arm/utility.hh" 49#include "arch/arm/system.hh" 50#include "base/trace.hh" 51#include "cpu/static_inst.hh" 52#include "sim/byteswap.hh" 53#include "sim/full_system.hh" 54 55namespace ArmISA 56{ 57 58class ArmStaticInst : public StaticInst 59{ 60 protected: 61 bool aarch64; 62 uint8_t intWidth; 63 64 int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 65 uint32_t type, uint32_t cfval) const; 66 int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 67 uint32_t type, uint32_t cfval) const; 68 69 bool shift_carry_imm(uint32_t base, uint32_t shamt, 70 uint32_t type, uint32_t cfval) const; 71 bool shift_carry_rs(uint32_t base, uint32_t shamt, 72 uint32_t type, uint32_t cfval) const; 73 74 int64_t shiftReg64(uint64_t base, uint64_t shiftAmt, 75 ArmShiftType type, uint8_t width) const; 76 int64_t extendReg64(uint64_t base, ArmExtendType type, 77 uint64_t shiftAmt, uint8_t width) const; 78 79 template<int width> 80 static inline bool 81 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) 82 { 83 int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 84 if (bits(midRes, width) != bits(midRes, width - 1)) { 85 if (midRes > 0) 86 res = (LL(1) << (width - 1)) - 1; 87 else 88 res = -(LL(1) << (width - 1)); 89 return true; 90 } else { 91 res = midRes; 92 return false; 93 } 94 } 95 96 static inline bool 97 satInt(int32_t &res, int64_t op, int width) 98 { 99 width--; 100 if (op >= (LL(1) << width)) { 101 res = (LL(1) << width) - 1; 102 return true; 103 } else if (op < -(LL(1) << width)) { 104 res = -(LL(1) << width); 105 return true; 106 } else { 107 res = op; 108 return false; 109 } 110 } 111 112 template<int width> 113 static inline bool 114 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) 115 { 116 int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 117 if (midRes >= (LL(1) << width)) { 118 res = (LL(1) << width) - 1; 119 return true; 120 } else if (midRes < 0) { 121 res = 0; 122 return true; 123 } else { 124 res = midRes; 125 return false; 126 } 127 } 128 129 static inline bool 130 uSatInt(int32_t &res, int64_t op, int width) 131 { 132 if (op >= (LL(1) << width)) { 133 res = (LL(1) << width) - 1; 134 return true; 135 } else if (op < 0) { 136 res = 0; 137 return true; 138 } else { 139 res = op; 140 return false; 141 } 142 } 143 144 // Constructor 145 ArmStaticInst(const char *mnem, ExtMachInst _machInst, 146 OpClass __opClass) 147 : StaticInst(mnem, _machInst, __opClass) 148 { 149 aarch64 = machInst.aarch64; 150 if (bits(machInst, 28, 24) == 0x10) 151 intWidth = 64; // Force 64-bit width for ADR/ADRP 152 else 153 intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32; 154 } 155 156 /// Print a register name for disassembly given the unique 157 /// dependence tag number (FP or int). 158 void printIntReg(std::ostream &os, RegIndex reg_idx) const; 159 void printFloatReg(std::ostream &os, RegIndex reg_idx) const; 160 void printVecReg(std::ostream &os, RegIndex reg_idx) const; 161 void printCCReg(std::ostream &os, RegIndex reg_idx) const; 162 void printMiscReg(std::ostream &os, RegIndex reg_idx) const; 163 void printMnemonic(std::ostream &os, 164 const std::string &suffix = "", 165 bool withPred = true, 166 bool withCond64 = false, 167 ConditionCode cond64 = COND_UC) const; 168 void printTarget(std::ostream &os, Addr target, 169 const SymbolTable *symtab) const; 170 void printCondition(std::ostream &os, unsigned code, 171 bool noImplicit=false) const; 172 void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 173 const std::string &prefix, const Addr addr, 174 const std::string &suffix) const; 175 void printShiftOperand(std::ostream &os, IntRegIndex rm, 176 bool immShift, uint32_t shiftAmt, 177 IntRegIndex rs, ArmShiftType type) const; 178 void printExtendOperand(bool firstOperand, std::ostream &os, 179 IntRegIndex rm, ArmExtendType type, 180 int64_t shiftAmt) const; 181 182 183 void printDataInst(std::ostream &os, bool withImm) const; 184 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 185 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 186 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 187 uint64_t imm) const; 188 189 void 190 advancePC(PCState &pcState) const 191 { 192 pcState.advance(); 193 } 194 195 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 196 197 static inline uint32_t 198 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, 199 uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc) 200 { 201 bool privileged = (cpsr.mode != MODE_USER); 202 bool haveVirt = ArmSystem::haveVirtualization(tc); 203 bool haveSecurity = ArmSystem::haveSecurity(tc); 204 bool isSecure = inSecureState(scr, cpsr) || !haveSecurity; 205 206 uint32_t bitMask = 0; 207 208 if (bits(byteMask, 3)) { 209 unsigned lowIdx = affectState ? 24 : 27; 210 bitMask = bitMask | mask(31, lowIdx); 211 } 212 if (bits(byteMask, 2)) { 213 bitMask = bitMask | mask(19, 16); 214 } 215 if (bits(byteMask, 1)) { 216 unsigned highIdx = affectState ? 15 : 9; 217 unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt)) 218 ? 8 : 9; 219 bitMask = bitMask | mask(highIdx, lowIdx); 220 } 221 if (bits(byteMask, 0)) { 222 if (privileged) { 223 bitMask |= 1 << 7; 224 if ( (!nmfi || !((val >> 6) & 0x1)) && 225 (isSecure || scr.fw || haveVirt) ) { 226 bitMask |= 1 << 6; 227 } 228 // Now check the new mode is allowed 229 OperatingMode newMode = (OperatingMode) (val & mask(5)); 230 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode; 231 if (!badMode(newMode)) { 232 bool validModeChange = true; 233 // Check for attempts to enter modes only permitted in 234 // Secure state from Non-secure state. These are Monitor 235 // mode ('10110'), and FIQ mode ('10001') if the Security 236 // Extensions have reserved it. 237 if (!isSecure && newMode == MODE_MON) 238 validModeChange = false; 239 if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1') 240 validModeChange = false; 241 // There is no Hyp mode ('11010') in Secure state, so that 242 // is UNPREDICTABLE 243 if (scr.ns == '0' && newMode == MODE_HYP) 244 validModeChange = false; 245 // Cannot move into Hyp mode directly from a Non-secure 246 // PL1 mode 247 if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP) 248 validModeChange = false; 249 // Cannot move out of Hyp mode with this function except 250 // on an exception return 251 if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState) 252 validModeChange = false; 253 // Must not change to 64 bit when running in 32 bit mode 254 if (!opModeIs64(oldMode) && opModeIs64(newMode)) 255 validModeChange = false; 256 257 // If we passed all of the above then set the bit mask to 258 // copy the mode accross 259 if (validModeChange) { 260 bitMask = bitMask | mask(5); 261 } else { 262 warn_once("Illegal change to CPSR mode attempted\n"); 263 } 264 } else { 265 warn_once("Ignoring write of bad mode to CPSR.\n"); 266 } 267 } 268 if (affectState) 269 bitMask = bitMask | (1 << 5); 270 } 271 272 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 273 } 274 275 static inline uint32_t 276 spsrWriteByInstr(uint32_t spsr, uint32_t val, 277 uint8_t byteMask, bool affectState) 278 { 279 uint32_t bitMask = 0; 280 281 if (bits(byteMask, 3)) 282 bitMask = bitMask | mask(31, 24); 283 if (bits(byteMask, 2)) 284 bitMask = bitMask | mask(19, 16); 285 if (bits(byteMask, 1)) 286 bitMask = bitMask | mask(15, 8); 287 if (bits(byteMask, 0)) 288 bitMask = bitMask | mask(7, 0); 289 290 return ((spsr & ~bitMask) | (val & bitMask)); 291 } 292 293 template<class XC> 294 static inline Addr 295 readPC(XC *xc) 296 { 297 return xc->pcState().instPC(); 298 } 299 300 template<class XC> 301 static inline void 302 setNextPC(XC *xc, Addr val) 303 { 304 PCState pc = xc->pcState(); 305 pc.instNPC(val); 306 xc->pcState(pc); 307 } 308 309 template<class T> 310 static inline T 311 cSwap(T val, bool big) 312 { 313 if (big) { 314 return gtobe(val); 315 } else { 316 return gtole(val); 317 } 318 } 319 320 template<class T, class E> 321 static inline T 322 cSwap(T val, bool big) 323 { 324 const unsigned count = sizeof(T) / sizeof(E); 325 union { 326 T tVal; 327 E eVals[count]; 328 } conv; 329 conv.tVal = htog(val); 330 if (big) { 331 for (unsigned i = 0; i < count; i++) { 332 conv.eVals[i] = gtobe(conv.eVals[i]); 333 } 334 } else { 335 for (unsigned i = 0; i < count; i++) { 336 conv.eVals[i] = gtole(conv.eVals[i]); 337 } 338 } 339 return gtoh(conv.tVal); 340 } 341 342 // Perform an interworking branch. 343 template<class XC> 344 static inline void 345 setIWNextPC(XC *xc, Addr val) 346 { 347 PCState pc = xc->pcState(); 348 pc.instIWNPC(val); 349 xc->pcState(pc); 350 } 351 352 // Perform an interworking branch in ARM mode, a regular branch 353 // otherwise. 354 template<class XC> 355 static inline void 356 setAIWNextPC(XC *xc, Addr val) 357 { 358 PCState pc = xc->pcState(); 359 pc.instAIWNPC(val); 360 xc->pcState(pc); 361 } 362 363 inline Fault 364 disabledFault() const 365 { 366 return std::make_shared<UndefinedInstruction>(machInst, false, 367 mnemonic, true); 368 } 369 370 /** 371 * Trap an access to Advanced SIMD or FP registers due to access 372 * control bits. 373 * 374 * See aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap in the 375 * ARM ARM psueodcode library. 376 * 377 * @param el Target EL for the trap 378 */ 379 Fault advSIMDFPAccessTrap64(ExceptionLevel el) const; 380 381 382 /** 383 * Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. 384 * 385 * See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap in the 386 * ARM ARM psueodcode library. 387 */ 388 Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const; 389 390 /** 391 * Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and 392 * CPTR_EL3. 393 * 394 * See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled in the 395 * ARM ARM psueodcode library. 396 */ 397 Fault checkFPAdvSIMDEnabled64(ThreadContext *tc, 398 CPSR cpsr, CPACR cpacr) const; 399 400 /** 401 * Check if a VFP/SIMD access from aarch32 should be allowed. 402 * 403 * See aarch32/exceptions/traps/AArch32.CheckAdvSIMDOrFPEnabled in the 404 * ARM ARM psueodcode library. 405 */ 406 Fault checkAdvSIMDOrFPEnabled32(ThreadContext *tc, 407 CPSR cpsr, CPACR cpacr, 408 NSACR nsacr, FPEXC fpexc, 409 bool fpexc_check, bool advsimd) const; 410 411 /** 412 * Get the new PSTATE from a SPSR register in preparation for an 413 * exception return. 414 * 415 * See shared/functions/system/SetPSTATEFromPSR in the ARM ARM 416 * psueodcode library. 417 */ 418 CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const; 419 420 public: 421 virtual void 422 annotateFault(ArmFault *fault) {} 423}; 424} 425 426#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 427