static_inst.hh revision 7720
17093Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 147093Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_INSTS_STATICINST_HH__ 446253Sgblack@eecs.umich.edu 457640Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 467692SAli.Saidi@ARM.com#include "arch/arm/utility.hh" 476253Sgblack@eecs.umich.edu#include "base/trace.hh" 486253Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 496253Sgblack@eecs.umich.edu 506253Sgblack@eecs.umich.edunamespace ArmISA 516253Sgblack@eecs.umich.edu{ 527424Sgblack@eecs.umich.edu 537148Sgblack@eecs.umich.educlass ArmStaticInst : public StaticInst 546254Sgblack@eecs.umich.edu{ 556254Sgblack@eecs.umich.edu protected: 566255Sgblack@eecs.umich.edu int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 576255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 586255Sgblack@eecs.umich.edu int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 596255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 606254Sgblack@eecs.umich.edu 616255Sgblack@eecs.umich.edu bool shift_carry_imm(uint32_t base, uint32_t shamt, 626255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 636255Sgblack@eecs.umich.edu bool shift_carry_rs(uint32_t base, uint32_t shamt, 646255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 656254Sgblack@eecs.umich.edu 667193Sgblack@eecs.umich.edu template<int width> 677424Sgblack@eecs.umich.edu static inline bool 687193Sgblack@eecs.umich.edu saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) 697193Sgblack@eecs.umich.edu { 707193Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 717193Sgblack@eecs.umich.edu if (bits(midRes, width) != bits(midRes, width - 1)) { 727193Sgblack@eecs.umich.edu if (midRes > 0) 737226Sgblack@eecs.umich.edu res = (LL(1) << (width - 1)) - 1; 747193Sgblack@eecs.umich.edu else 757226Sgblack@eecs.umich.edu res = -(LL(1) << (width - 1)); 767193Sgblack@eecs.umich.edu return true; 777193Sgblack@eecs.umich.edu } else { 787193Sgblack@eecs.umich.edu res = midRes; 797193Sgblack@eecs.umich.edu return false; 807193Sgblack@eecs.umich.edu } 817193Sgblack@eecs.umich.edu } 827193Sgblack@eecs.umich.edu 837424Sgblack@eecs.umich.edu static inline bool 847226Sgblack@eecs.umich.edu satInt(int32_t &res, int64_t op, int width) 857226Sgblack@eecs.umich.edu { 867226Sgblack@eecs.umich.edu width--; 877226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 887226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 897226Sgblack@eecs.umich.edu return true; 907226Sgblack@eecs.umich.edu } else if (op < -(LL(1) << width)) { 917226Sgblack@eecs.umich.edu res = -(LL(1) << width); 927226Sgblack@eecs.umich.edu return true; 937226Sgblack@eecs.umich.edu } else { 947226Sgblack@eecs.umich.edu res = op; 957226Sgblack@eecs.umich.edu return false; 967226Sgblack@eecs.umich.edu } 977226Sgblack@eecs.umich.edu } 987226Sgblack@eecs.umich.edu 997219Sgblack@eecs.umich.edu template<int width> 1007424Sgblack@eecs.umich.edu static inline bool 1017219Sgblack@eecs.umich.edu uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) 1027219Sgblack@eecs.umich.edu { 1037219Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 1047226Sgblack@eecs.umich.edu if (midRes >= (LL(1) << width)) { 1057226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1067219Sgblack@eecs.umich.edu return true; 1077219Sgblack@eecs.umich.edu } else if (midRes < 0) { 1087219Sgblack@eecs.umich.edu res = 0; 1097219Sgblack@eecs.umich.edu return true; 1107219Sgblack@eecs.umich.edu } else { 1117219Sgblack@eecs.umich.edu res = midRes; 1127219Sgblack@eecs.umich.edu return false; 1137219Sgblack@eecs.umich.edu } 1147219Sgblack@eecs.umich.edu } 1157219Sgblack@eecs.umich.edu 1167424Sgblack@eecs.umich.edu static inline bool 1177226Sgblack@eecs.umich.edu uSatInt(int32_t &res, int64_t op, int width) 1187226Sgblack@eecs.umich.edu { 1197226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 1207226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1217226Sgblack@eecs.umich.edu return true; 1227226Sgblack@eecs.umich.edu } else if (op < 0) { 1237226Sgblack@eecs.umich.edu res = 0; 1247226Sgblack@eecs.umich.edu return true; 1257226Sgblack@eecs.umich.edu } else { 1267226Sgblack@eecs.umich.edu res = op; 1277226Sgblack@eecs.umich.edu return false; 1287226Sgblack@eecs.umich.edu } 1297226Sgblack@eecs.umich.edu } 1307226Sgblack@eecs.umich.edu 1316254Sgblack@eecs.umich.edu // Constructor 1327148Sgblack@eecs.umich.edu ArmStaticInst(const char *mnem, ExtMachInst _machInst, 1337148Sgblack@eecs.umich.edu OpClass __opClass) 1346254Sgblack@eecs.umich.edu : StaticInst(mnem, _machInst, __opClass) 1356253Sgblack@eecs.umich.edu { 1366254Sgblack@eecs.umich.edu } 1376253Sgblack@eecs.umich.edu 1386254Sgblack@eecs.umich.edu /// Print a register name for disassembly given the unique 1396254Sgblack@eecs.umich.edu /// dependence tag number (FP or int). 1406254Sgblack@eecs.umich.edu void printReg(std::ostream &os, int reg) const; 1416262Sgblack@eecs.umich.edu void printMnemonic(std::ostream &os, 1426262Sgblack@eecs.umich.edu const std::string &suffix = "", 1436262Sgblack@eecs.umich.edu bool withPred = true) const; 1446263Sgblack@eecs.umich.edu void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 1456263Sgblack@eecs.umich.edu const std::string &prefix, const Addr addr, 1466263Sgblack@eecs.umich.edu const std::string &suffix) const; 1477142Sgblack@eecs.umich.edu void printShiftOperand(std::ostream &os, IntRegIndex rm, 1487142Sgblack@eecs.umich.edu bool immShift, uint32_t shiftAmt, 1497142Sgblack@eecs.umich.edu IntRegIndex rs, ArmShiftType type) const; 1506263Sgblack@eecs.umich.edu 1516253Sgblack@eecs.umich.edu 1526306Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm) const; 1537142Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 1547142Sgblack@eecs.umich.edu IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 1557142Sgblack@eecs.umich.edu IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 1567142Sgblack@eecs.umich.edu uint32_t imm) const; 1576264Sgblack@eecs.umich.edu 1587720Sgblack@eecs.umich.edu void 1597720Sgblack@eecs.umich.edu advancePC(PCState &pcState) const 1607720Sgblack@eecs.umich.edu { 1617720Sgblack@eecs.umich.edu pcState.advance(); 1627720Sgblack@eecs.umich.edu } 1637720Sgblack@eecs.umich.edu 1646254Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1656748Sgblack@eecs.umich.edu 1667424Sgblack@eecs.umich.edu static inline uint32_t 1676748Sgblack@eecs.umich.edu cpsrWriteByInstr(CPSR cpsr, uint32_t val, 1687400SAli.Saidi@ARM.com uint8_t byteMask, bool affectState, bool nmfi) 1696748Sgblack@eecs.umich.edu { 1706748Sgblack@eecs.umich.edu bool privileged = (cpsr.mode != MODE_USER); 1716748Sgblack@eecs.umich.edu 1726748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 1736748Sgblack@eecs.umich.edu 1746748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) { 1756748Sgblack@eecs.umich.edu unsigned lowIdx = affectState ? 24 : 27; 1766748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, lowIdx); 1776748Sgblack@eecs.umich.edu } 1786748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) { 1796748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 1806748Sgblack@eecs.umich.edu } 1816748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) { 1826748Sgblack@eecs.umich.edu unsigned highIdx = affectState ? 15 : 9; 1836748Sgblack@eecs.umich.edu unsigned lowIdx = privileged ? 8 : 9; 1846748Sgblack@eecs.umich.edu bitMask = bitMask | mask(highIdx, lowIdx); 1856748Sgblack@eecs.umich.edu } 1866748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) { 1876748Sgblack@eecs.umich.edu if (privileged) { 1886748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 6); 1897317Sgblack@eecs.umich.edu if (!badMode((OperatingMode)(val & mask(5)))) { 1907317Sgblack@eecs.umich.edu bitMask = bitMask | mask(5); 1917317Sgblack@eecs.umich.edu } else { 1927317Sgblack@eecs.umich.edu warn_once("Ignoring write of bad mode to CPSR.\n"); 1937317Sgblack@eecs.umich.edu } 1946748Sgblack@eecs.umich.edu } 1956748Sgblack@eecs.umich.edu if (affectState) 1966748Sgblack@eecs.umich.edu bitMask = bitMask | (1 << 5); 1976748Sgblack@eecs.umich.edu } 1986748Sgblack@eecs.umich.edu 1997400SAli.Saidi@ARM.com bool cpsr_f = cpsr.f; 2007400SAli.Saidi@ARM.com uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 2017400SAli.Saidi@ARM.com if (nmfi && !cpsr_f) 2027400SAli.Saidi@ARM.com new_cpsr &= ~(1 << 6); 2037400SAli.Saidi@ARM.com return new_cpsr; 2046748Sgblack@eecs.umich.edu } 2056748Sgblack@eecs.umich.edu 2067424Sgblack@eecs.umich.edu static inline uint32_t 2076748Sgblack@eecs.umich.edu spsrWriteByInstr(uint32_t spsr, uint32_t val, 2086748Sgblack@eecs.umich.edu uint8_t byteMask, bool affectState) 2096748Sgblack@eecs.umich.edu { 2106748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 2116748Sgblack@eecs.umich.edu 2126748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) 2136748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, 24); 2146748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) 2156748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 2166748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) 2176748Sgblack@eecs.umich.edu bitMask = bitMask | mask(15, 8); 2186748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) 2196748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 0); 2206748Sgblack@eecs.umich.edu 2216748Sgblack@eecs.umich.edu return ((spsr & ~bitMask) | (val & bitMask)); 2226748Sgblack@eecs.umich.edu } 2237093Sgblack@eecs.umich.edu 2247093Sgblack@eecs.umich.edu template<class XC> 2257424Sgblack@eecs.umich.edu static inline Addr 2267147Sgblack@eecs.umich.edu readPC(XC *xc) 2277147Sgblack@eecs.umich.edu { 2287720Sgblack@eecs.umich.edu return xc->pcState().instPC(); 2297147Sgblack@eecs.umich.edu } 2307147Sgblack@eecs.umich.edu 2317147Sgblack@eecs.umich.edu template<class XC> 2327424Sgblack@eecs.umich.edu static inline void 2337093Sgblack@eecs.umich.edu setNextPC(XC *xc, Addr val) 2347093Sgblack@eecs.umich.edu { 2357720Sgblack@eecs.umich.edu PCState pc = xc->pcState(); 2367720Sgblack@eecs.umich.edu pc.instNPC(val); 2377720Sgblack@eecs.umich.edu xc->pcState(pc); 2387093Sgblack@eecs.umich.edu } 2397094Sgblack@eecs.umich.edu 2407296Sgblack@eecs.umich.edu template<class T> 2417424Sgblack@eecs.umich.edu static inline T 2427296Sgblack@eecs.umich.edu cSwap(T val, bool big) 2437296Sgblack@eecs.umich.edu { 2447296Sgblack@eecs.umich.edu if (big) { 2457296Sgblack@eecs.umich.edu return gtobe(val); 2467296Sgblack@eecs.umich.edu } else { 2477296Sgblack@eecs.umich.edu return gtole(val); 2487296Sgblack@eecs.umich.edu } 2497296Sgblack@eecs.umich.edu } 2507296Sgblack@eecs.umich.edu 2517639Sgblack@eecs.umich.edu template<class T, class E> 2527639Sgblack@eecs.umich.edu static inline T 2537639Sgblack@eecs.umich.edu cSwap(T val, bool big) 2547639Sgblack@eecs.umich.edu { 2557639Sgblack@eecs.umich.edu const unsigned count = sizeof(T) / sizeof(E); 2567639Sgblack@eecs.umich.edu union { 2577639Sgblack@eecs.umich.edu T tVal; 2587639Sgblack@eecs.umich.edu E eVals[count]; 2597639Sgblack@eecs.umich.edu } conv; 2607639Sgblack@eecs.umich.edu conv.tVal = htog(val); 2617639Sgblack@eecs.umich.edu if (big) { 2627639Sgblack@eecs.umich.edu for (unsigned i = 0; i < count; i++) { 2637639Sgblack@eecs.umich.edu conv.eVals[i] = gtobe(conv.eVals[i]); 2647639Sgblack@eecs.umich.edu } 2657639Sgblack@eecs.umich.edu } else { 2667639Sgblack@eecs.umich.edu for (unsigned i = 0; i < count; i++) { 2677639Sgblack@eecs.umich.edu conv.eVals[i] = gtole(conv.eVals[i]); 2687639Sgblack@eecs.umich.edu } 2697639Sgblack@eecs.umich.edu } 2707639Sgblack@eecs.umich.edu return gtoh(conv.tVal); 2717639Sgblack@eecs.umich.edu } 2727639Sgblack@eecs.umich.edu 2737148Sgblack@eecs.umich.edu // Perform an interworking branch. 2747094Sgblack@eecs.umich.edu template<class XC> 2757424Sgblack@eecs.umich.edu static inline void 2767148Sgblack@eecs.umich.edu setIWNextPC(XC *xc, Addr val) 2777094Sgblack@eecs.umich.edu { 2787720Sgblack@eecs.umich.edu PCState pc = xc->pcState(); 2797720Sgblack@eecs.umich.edu pc.instIWNPC(val); 2807720Sgblack@eecs.umich.edu xc->pcState(pc); 2817094Sgblack@eecs.umich.edu } 2827148Sgblack@eecs.umich.edu 2837148Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 2847148Sgblack@eecs.umich.edu // otherwise. 2857148Sgblack@eecs.umich.edu template<class XC> 2867424Sgblack@eecs.umich.edu static inline void 2877148Sgblack@eecs.umich.edu setAIWNextPC(XC *xc, Addr val) 2887148Sgblack@eecs.umich.edu { 2897720Sgblack@eecs.umich.edu PCState pc = xc->pcState(); 2907720Sgblack@eecs.umich.edu pc.instAIWNPC(val); 2917720Sgblack@eecs.umich.edu xc->pcState(pc); 2927148Sgblack@eecs.umich.edu } 2937640Sgblack@eecs.umich.edu 2947640Sgblack@eecs.umich.edu inline Fault 2957640Sgblack@eecs.umich.edu disabledFault() const 2967640Sgblack@eecs.umich.edu { 2977640Sgblack@eecs.umich.edu#if FULL_SYSTEM 2987640Sgblack@eecs.umich.edu return new UndefinedInstruction(); 2997640Sgblack@eecs.umich.edu#else 3007640Sgblack@eecs.umich.edu return new UndefinedInstruction(machInst, false, mnemonic, true); 3017640Sgblack@eecs.umich.edu#endif 3027640Sgblack@eecs.umich.edu } 3037094Sgblack@eecs.umich.edu}; 3046253Sgblack@eecs.umich.edu} 3056253Sgblack@eecs.umich.edu 3066253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 307