static_inst.hh revision 7424
17093Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 147093Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_INSTS_STATICINST_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "base/trace.hh" 466253Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 476253Sgblack@eecs.umich.edu 486253Sgblack@eecs.umich.edunamespace ArmISA 496253Sgblack@eecs.umich.edu{ 507424Sgblack@eecs.umich.edu 517148Sgblack@eecs.umich.educlass ArmStaticInst : public StaticInst 526254Sgblack@eecs.umich.edu{ 536254Sgblack@eecs.umich.edu protected: 546255Sgblack@eecs.umich.edu int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 556255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 566255Sgblack@eecs.umich.edu int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 576255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 586254Sgblack@eecs.umich.edu 596255Sgblack@eecs.umich.edu bool shift_carry_imm(uint32_t base, uint32_t shamt, 606255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 616255Sgblack@eecs.umich.edu bool shift_carry_rs(uint32_t base, uint32_t shamt, 626255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 636254Sgblack@eecs.umich.edu 647193Sgblack@eecs.umich.edu template<int width> 657424Sgblack@eecs.umich.edu static inline bool 667193Sgblack@eecs.umich.edu saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) 677193Sgblack@eecs.umich.edu { 687193Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 697193Sgblack@eecs.umich.edu if (bits(midRes, width) != bits(midRes, width - 1)) { 707193Sgblack@eecs.umich.edu if (midRes > 0) 717226Sgblack@eecs.umich.edu res = (LL(1) << (width - 1)) - 1; 727193Sgblack@eecs.umich.edu else 737226Sgblack@eecs.umich.edu res = -(LL(1) << (width - 1)); 747193Sgblack@eecs.umich.edu return true; 757193Sgblack@eecs.umich.edu } else { 767193Sgblack@eecs.umich.edu res = midRes; 777193Sgblack@eecs.umich.edu return false; 787193Sgblack@eecs.umich.edu } 797193Sgblack@eecs.umich.edu } 807193Sgblack@eecs.umich.edu 817424Sgblack@eecs.umich.edu static inline bool 827226Sgblack@eecs.umich.edu satInt(int32_t &res, int64_t op, int width) 837226Sgblack@eecs.umich.edu { 847226Sgblack@eecs.umich.edu width--; 857226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 867226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 877226Sgblack@eecs.umich.edu return true; 887226Sgblack@eecs.umich.edu } else if (op < -(LL(1) << width)) { 897226Sgblack@eecs.umich.edu res = -(LL(1) << width); 907226Sgblack@eecs.umich.edu return true; 917226Sgblack@eecs.umich.edu } else { 927226Sgblack@eecs.umich.edu res = op; 937226Sgblack@eecs.umich.edu return false; 947226Sgblack@eecs.umich.edu } 957226Sgblack@eecs.umich.edu } 967226Sgblack@eecs.umich.edu 977219Sgblack@eecs.umich.edu template<int width> 987424Sgblack@eecs.umich.edu static inline bool 997219Sgblack@eecs.umich.edu uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) 1007219Sgblack@eecs.umich.edu { 1017219Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 1027226Sgblack@eecs.umich.edu if (midRes >= (LL(1) << width)) { 1037226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1047219Sgblack@eecs.umich.edu return true; 1057219Sgblack@eecs.umich.edu } else if (midRes < 0) { 1067219Sgblack@eecs.umich.edu res = 0; 1077219Sgblack@eecs.umich.edu return true; 1087219Sgblack@eecs.umich.edu } else { 1097219Sgblack@eecs.umich.edu res = midRes; 1107219Sgblack@eecs.umich.edu return false; 1117219Sgblack@eecs.umich.edu } 1127219Sgblack@eecs.umich.edu } 1137219Sgblack@eecs.umich.edu 1147424Sgblack@eecs.umich.edu static inline bool 1157226Sgblack@eecs.umich.edu uSatInt(int32_t &res, int64_t op, int width) 1167226Sgblack@eecs.umich.edu { 1177226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 1187226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1197226Sgblack@eecs.umich.edu return true; 1207226Sgblack@eecs.umich.edu } else if (op < 0) { 1217226Sgblack@eecs.umich.edu res = 0; 1227226Sgblack@eecs.umich.edu return true; 1237226Sgblack@eecs.umich.edu } else { 1247226Sgblack@eecs.umich.edu res = op; 1257226Sgblack@eecs.umich.edu return false; 1267226Sgblack@eecs.umich.edu } 1277226Sgblack@eecs.umich.edu } 1287226Sgblack@eecs.umich.edu 1296254Sgblack@eecs.umich.edu // Constructor 1307148Sgblack@eecs.umich.edu ArmStaticInst(const char *mnem, ExtMachInst _machInst, 1317148Sgblack@eecs.umich.edu OpClass __opClass) 1326254Sgblack@eecs.umich.edu : StaticInst(mnem, _machInst, __opClass) 1336253Sgblack@eecs.umich.edu { 1346254Sgblack@eecs.umich.edu } 1356253Sgblack@eecs.umich.edu 1366254Sgblack@eecs.umich.edu /// Print a register name for disassembly given the unique 1376254Sgblack@eecs.umich.edu /// dependence tag number (FP or int). 1386254Sgblack@eecs.umich.edu void printReg(std::ostream &os, int reg) const; 1396262Sgblack@eecs.umich.edu void printMnemonic(std::ostream &os, 1406262Sgblack@eecs.umich.edu const std::string &suffix = "", 1416262Sgblack@eecs.umich.edu bool withPred = true) const; 1426263Sgblack@eecs.umich.edu void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 1436263Sgblack@eecs.umich.edu const std::string &prefix, const Addr addr, 1446263Sgblack@eecs.umich.edu const std::string &suffix) const; 1457142Sgblack@eecs.umich.edu void printShiftOperand(std::ostream &os, IntRegIndex rm, 1467142Sgblack@eecs.umich.edu bool immShift, uint32_t shiftAmt, 1477142Sgblack@eecs.umich.edu IntRegIndex rs, ArmShiftType type) const; 1486263Sgblack@eecs.umich.edu 1496253Sgblack@eecs.umich.edu 1506306Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm) const; 1517142Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 1527142Sgblack@eecs.umich.edu IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 1537142Sgblack@eecs.umich.edu IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 1547142Sgblack@eecs.umich.edu uint32_t imm) const; 1556264Sgblack@eecs.umich.edu 1566254Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1576748Sgblack@eecs.umich.edu 1587424Sgblack@eecs.umich.edu static inline uint32_t 1596748Sgblack@eecs.umich.edu cpsrWriteByInstr(CPSR cpsr, uint32_t val, 1607400SAli.Saidi@ARM.com uint8_t byteMask, bool affectState, bool nmfi) 1616748Sgblack@eecs.umich.edu { 1626748Sgblack@eecs.umich.edu bool privileged = (cpsr.mode != MODE_USER); 1636748Sgblack@eecs.umich.edu 1646748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 1656748Sgblack@eecs.umich.edu 1666748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) { 1676748Sgblack@eecs.umich.edu unsigned lowIdx = affectState ? 24 : 27; 1686748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, lowIdx); 1696748Sgblack@eecs.umich.edu } 1706748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) { 1716748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 1726748Sgblack@eecs.umich.edu } 1736748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) { 1746748Sgblack@eecs.umich.edu unsigned highIdx = affectState ? 15 : 9; 1756748Sgblack@eecs.umich.edu unsigned lowIdx = privileged ? 8 : 9; 1766748Sgblack@eecs.umich.edu bitMask = bitMask | mask(highIdx, lowIdx); 1776748Sgblack@eecs.umich.edu } 1786748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) { 1796748Sgblack@eecs.umich.edu if (privileged) { 1806748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 6); 1817317Sgblack@eecs.umich.edu if (!badMode((OperatingMode)(val & mask(5)))) { 1827317Sgblack@eecs.umich.edu bitMask = bitMask | mask(5); 1837317Sgblack@eecs.umich.edu } else { 1847317Sgblack@eecs.umich.edu warn_once("Ignoring write of bad mode to CPSR.\n"); 1857317Sgblack@eecs.umich.edu } 1866748Sgblack@eecs.umich.edu } 1876748Sgblack@eecs.umich.edu if (affectState) 1886748Sgblack@eecs.umich.edu bitMask = bitMask | (1 << 5); 1896748Sgblack@eecs.umich.edu } 1906748Sgblack@eecs.umich.edu 1917400SAli.Saidi@ARM.com bool cpsr_f = cpsr.f; 1927400SAli.Saidi@ARM.com uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 1937400SAli.Saidi@ARM.com if (nmfi && !cpsr_f) 1947400SAli.Saidi@ARM.com new_cpsr &= ~(1 << 6); 1957400SAli.Saidi@ARM.com return new_cpsr; 1966748Sgblack@eecs.umich.edu } 1976748Sgblack@eecs.umich.edu 1987424Sgblack@eecs.umich.edu static inline uint32_t 1996748Sgblack@eecs.umich.edu spsrWriteByInstr(uint32_t spsr, uint32_t val, 2006748Sgblack@eecs.umich.edu uint8_t byteMask, bool affectState) 2016748Sgblack@eecs.umich.edu { 2026748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 2036748Sgblack@eecs.umich.edu 2046748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) 2056748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, 24); 2066748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) 2076748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 2086748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) 2096748Sgblack@eecs.umich.edu bitMask = bitMask | mask(15, 8); 2106748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) 2116748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 0); 2126748Sgblack@eecs.umich.edu 2136748Sgblack@eecs.umich.edu return ((spsr & ~bitMask) | (val & bitMask)); 2146748Sgblack@eecs.umich.edu } 2157093Sgblack@eecs.umich.edu 2167093Sgblack@eecs.umich.edu template<class XC> 2177424Sgblack@eecs.umich.edu static inline Addr 2187147Sgblack@eecs.umich.edu readPC(XC *xc) 2197147Sgblack@eecs.umich.edu { 2207147Sgblack@eecs.umich.edu Addr pc = xc->readPC(); 2217147Sgblack@eecs.umich.edu Addr tBit = pc & (ULL(1) << PcTBitShift); 2227147Sgblack@eecs.umich.edu if (tBit) 2237147Sgblack@eecs.umich.edu return pc + 4; 2247147Sgblack@eecs.umich.edu else 2257147Sgblack@eecs.umich.edu return pc + 8; 2267147Sgblack@eecs.umich.edu } 2277147Sgblack@eecs.umich.edu 2287148Sgblack@eecs.umich.edu // Perform an regular branch. 2297147Sgblack@eecs.umich.edu template<class XC> 2307424Sgblack@eecs.umich.edu static inline void 2317093Sgblack@eecs.umich.edu setNextPC(XC *xc, Addr val) 2327093Sgblack@eecs.umich.edu { 2337289Sgblack@eecs.umich.edu Addr npc = xc->readNextPC(); 2347289Sgblack@eecs.umich.edu if (npc & (ULL(1) << PcTBitShift)) { 2357289Sgblack@eecs.umich.edu val &= ~mask(1); 2367289Sgblack@eecs.umich.edu } else { 2377289Sgblack@eecs.umich.edu val &= ~mask(2); 2387289Sgblack@eecs.umich.edu } 2397289Sgblack@eecs.umich.edu xc->setNextPC((npc & PcModeMask) | 2407093Sgblack@eecs.umich.edu (val & ~PcModeMask)); 2417093Sgblack@eecs.umich.edu } 2427094Sgblack@eecs.umich.edu 2437296Sgblack@eecs.umich.edu template<class T> 2447424Sgblack@eecs.umich.edu static inline T 2457296Sgblack@eecs.umich.edu cSwap(T val, bool big) 2467296Sgblack@eecs.umich.edu { 2477296Sgblack@eecs.umich.edu if (big) { 2487296Sgblack@eecs.umich.edu return gtobe(val); 2497296Sgblack@eecs.umich.edu } else { 2507296Sgblack@eecs.umich.edu return gtole(val); 2517296Sgblack@eecs.umich.edu } 2527296Sgblack@eecs.umich.edu } 2537296Sgblack@eecs.umich.edu 2547148Sgblack@eecs.umich.edu // Perform an interworking branch. 2557094Sgblack@eecs.umich.edu template<class XC> 2567424Sgblack@eecs.umich.edu static inline void 2577148Sgblack@eecs.umich.edu setIWNextPC(XC *xc, Addr val) 2587094Sgblack@eecs.umich.edu { 2597094Sgblack@eecs.umich.edu Addr stateBits = xc->readPC() & PcModeMask; 2607094Sgblack@eecs.umich.edu Addr jBit = (ULL(1) << PcJBitShift); 2617094Sgblack@eecs.umich.edu Addr tBit = (ULL(1) << PcTBitShift); 2627094Sgblack@eecs.umich.edu bool thumbEE = (stateBits == (tBit | jBit)); 2637094Sgblack@eecs.umich.edu 2647094Sgblack@eecs.umich.edu Addr newPc = (val & ~PcModeMask); 2657094Sgblack@eecs.umich.edu if (thumbEE) { 2667094Sgblack@eecs.umich.edu if (bits(newPc, 0)) { 2677282Sgblack@eecs.umich.edu newPc = newPc & ~mask(1); 2687094Sgblack@eecs.umich.edu } else { 2697282Sgblack@eecs.umich.edu panic("Bad thumbEE interworking branch address %#x.\n", newPc); 2707094Sgblack@eecs.umich.edu } 2717094Sgblack@eecs.umich.edu } else { 2727094Sgblack@eecs.umich.edu if (bits(newPc, 0)) { 2737094Sgblack@eecs.umich.edu stateBits = tBit; 2747094Sgblack@eecs.umich.edu newPc = newPc & ~mask(1); 2757094Sgblack@eecs.umich.edu } else if (!bits(newPc, 1)) { 2767094Sgblack@eecs.umich.edu stateBits = 0; 2777094Sgblack@eecs.umich.edu } else { 2787094Sgblack@eecs.umich.edu warn("Bad interworking branch address %#x.\n", newPc); 2797094Sgblack@eecs.umich.edu } 2807094Sgblack@eecs.umich.edu } 2817094Sgblack@eecs.umich.edu newPc = newPc | stateBits; 2827094Sgblack@eecs.umich.edu xc->setNextPC(newPc); 2837094Sgblack@eecs.umich.edu } 2847148Sgblack@eecs.umich.edu 2857148Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 2867148Sgblack@eecs.umich.edu // otherwise. 2877148Sgblack@eecs.umich.edu template<class XC> 2887424Sgblack@eecs.umich.edu static inline void 2897148Sgblack@eecs.umich.edu setAIWNextPC(XC *xc, Addr val) 2907148Sgblack@eecs.umich.edu { 2917148Sgblack@eecs.umich.edu Addr stateBits = xc->readPC() & PcModeMask; 2927148Sgblack@eecs.umich.edu Addr jBit = (ULL(1) << PcJBitShift); 2937148Sgblack@eecs.umich.edu Addr tBit = (ULL(1) << PcTBitShift); 2947148Sgblack@eecs.umich.edu if (!jBit && !tBit) { 2957148Sgblack@eecs.umich.edu setIWNextPC(xc, val); 2967148Sgblack@eecs.umich.edu } else { 2977148Sgblack@eecs.umich.edu setNextPC(xc, val); 2987148Sgblack@eecs.umich.edu } 2997148Sgblack@eecs.umich.edu } 3007094Sgblack@eecs.umich.edu}; 3016253Sgblack@eecs.umich.edu} 3026253Sgblack@eecs.umich.edu 3036253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 304