static_inst.hh revision 7282
17093Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 147093Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_INSTS_STATICINST_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "base/trace.hh" 466253Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 476253Sgblack@eecs.umich.edu 486253Sgblack@eecs.umich.edunamespace ArmISA 496253Sgblack@eecs.umich.edu{ 507148Sgblack@eecs.umich.educlass ArmStaticInst : public StaticInst 516254Sgblack@eecs.umich.edu{ 526254Sgblack@eecs.umich.edu protected: 536255Sgblack@eecs.umich.edu int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 546255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 556255Sgblack@eecs.umich.edu int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 566255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 576254Sgblack@eecs.umich.edu 586255Sgblack@eecs.umich.edu bool shift_carry_imm(uint32_t base, uint32_t shamt, 596255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 606255Sgblack@eecs.umich.edu bool shift_carry_rs(uint32_t base, uint32_t shamt, 616255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 626254Sgblack@eecs.umich.edu 637193Sgblack@eecs.umich.edu template<int width> 647193Sgblack@eecs.umich.edu static bool 657193Sgblack@eecs.umich.edu saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) 667193Sgblack@eecs.umich.edu { 677193Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 687193Sgblack@eecs.umich.edu if (bits(midRes, width) != bits(midRes, width - 1)) { 697193Sgblack@eecs.umich.edu if (midRes > 0) 707226Sgblack@eecs.umich.edu res = (LL(1) << (width - 1)) - 1; 717193Sgblack@eecs.umich.edu else 727226Sgblack@eecs.umich.edu res = -(LL(1) << (width - 1)); 737193Sgblack@eecs.umich.edu return true; 747193Sgblack@eecs.umich.edu } else { 757193Sgblack@eecs.umich.edu res = midRes; 767193Sgblack@eecs.umich.edu return false; 777193Sgblack@eecs.umich.edu } 787193Sgblack@eecs.umich.edu } 797193Sgblack@eecs.umich.edu 807226Sgblack@eecs.umich.edu static bool 817226Sgblack@eecs.umich.edu satInt(int32_t &res, int64_t op, int width) 827226Sgblack@eecs.umich.edu { 837226Sgblack@eecs.umich.edu width--; 847226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 857226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 867226Sgblack@eecs.umich.edu return true; 877226Sgblack@eecs.umich.edu } else if (op < -(LL(1) << width)) { 887226Sgblack@eecs.umich.edu res = -(LL(1) << width); 897226Sgblack@eecs.umich.edu return true; 907226Sgblack@eecs.umich.edu } else { 917226Sgblack@eecs.umich.edu res = op; 927226Sgblack@eecs.umich.edu return false; 937226Sgblack@eecs.umich.edu } 947226Sgblack@eecs.umich.edu } 957226Sgblack@eecs.umich.edu 967219Sgblack@eecs.umich.edu template<int width> 977219Sgblack@eecs.umich.edu static bool 987219Sgblack@eecs.umich.edu uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) 997219Sgblack@eecs.umich.edu { 1007219Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 1017226Sgblack@eecs.umich.edu if (midRes >= (LL(1) << width)) { 1027226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1037219Sgblack@eecs.umich.edu return true; 1047219Sgblack@eecs.umich.edu } else if (midRes < 0) { 1057219Sgblack@eecs.umich.edu res = 0; 1067219Sgblack@eecs.umich.edu return true; 1077219Sgblack@eecs.umich.edu } else { 1087219Sgblack@eecs.umich.edu res = midRes; 1097219Sgblack@eecs.umich.edu return false; 1107219Sgblack@eecs.umich.edu } 1117219Sgblack@eecs.umich.edu } 1127219Sgblack@eecs.umich.edu 1137226Sgblack@eecs.umich.edu static bool 1147226Sgblack@eecs.umich.edu uSatInt(int32_t &res, int64_t op, int width) 1157226Sgblack@eecs.umich.edu { 1167226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 1177226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1187226Sgblack@eecs.umich.edu return true; 1197226Sgblack@eecs.umich.edu } else if (op < 0) { 1207226Sgblack@eecs.umich.edu res = 0; 1217226Sgblack@eecs.umich.edu return true; 1227226Sgblack@eecs.umich.edu } else { 1237226Sgblack@eecs.umich.edu res = op; 1247226Sgblack@eecs.umich.edu return false; 1257226Sgblack@eecs.umich.edu } 1267226Sgblack@eecs.umich.edu } 1277226Sgblack@eecs.umich.edu 1286254Sgblack@eecs.umich.edu // Constructor 1297148Sgblack@eecs.umich.edu ArmStaticInst(const char *mnem, ExtMachInst _machInst, 1307148Sgblack@eecs.umich.edu OpClass __opClass) 1316254Sgblack@eecs.umich.edu : StaticInst(mnem, _machInst, __opClass) 1326253Sgblack@eecs.umich.edu { 1336254Sgblack@eecs.umich.edu } 1346253Sgblack@eecs.umich.edu 1356254Sgblack@eecs.umich.edu /// Print a register name for disassembly given the unique 1366254Sgblack@eecs.umich.edu /// dependence tag number (FP or int). 1376254Sgblack@eecs.umich.edu void printReg(std::ostream &os, int reg) const; 1386262Sgblack@eecs.umich.edu void printMnemonic(std::ostream &os, 1396262Sgblack@eecs.umich.edu const std::string &suffix = "", 1406262Sgblack@eecs.umich.edu bool withPred = true) const; 1416263Sgblack@eecs.umich.edu void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 1426263Sgblack@eecs.umich.edu const std::string &prefix, const Addr addr, 1436263Sgblack@eecs.umich.edu const std::string &suffix) const; 1447142Sgblack@eecs.umich.edu void printShiftOperand(std::ostream &os, IntRegIndex rm, 1457142Sgblack@eecs.umich.edu bool immShift, uint32_t shiftAmt, 1467142Sgblack@eecs.umich.edu IntRegIndex rs, ArmShiftType type) const; 1476263Sgblack@eecs.umich.edu 1486253Sgblack@eecs.umich.edu 1496306Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm) const; 1507142Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 1517142Sgblack@eecs.umich.edu IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 1527142Sgblack@eecs.umich.edu IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 1537142Sgblack@eecs.umich.edu uint32_t imm) const; 1546264Sgblack@eecs.umich.edu 1556254Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1566748Sgblack@eecs.umich.edu 1576748Sgblack@eecs.umich.edu static uint32_t 1586748Sgblack@eecs.umich.edu cpsrWriteByInstr(CPSR cpsr, uint32_t val, 1596748Sgblack@eecs.umich.edu uint8_t byteMask, bool affectState) 1606748Sgblack@eecs.umich.edu { 1616748Sgblack@eecs.umich.edu bool privileged = (cpsr.mode != MODE_USER); 1626748Sgblack@eecs.umich.edu 1636748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 1646748Sgblack@eecs.umich.edu 1656748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) { 1666748Sgblack@eecs.umich.edu unsigned lowIdx = affectState ? 24 : 27; 1676748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, lowIdx); 1686748Sgblack@eecs.umich.edu } 1696748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) { 1706748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 1716748Sgblack@eecs.umich.edu } 1726748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) { 1736748Sgblack@eecs.umich.edu unsigned highIdx = affectState ? 15 : 9; 1746748Sgblack@eecs.umich.edu unsigned lowIdx = privileged ? 8 : 9; 1756748Sgblack@eecs.umich.edu bitMask = bitMask | mask(highIdx, lowIdx); 1766748Sgblack@eecs.umich.edu } 1776748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) { 1786748Sgblack@eecs.umich.edu if (privileged) { 1796748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 6); 1806748Sgblack@eecs.umich.edu bitMask = bitMask | mask(5); 1816748Sgblack@eecs.umich.edu } 1826748Sgblack@eecs.umich.edu if (affectState) 1836748Sgblack@eecs.umich.edu bitMask = bitMask | (1 << 5); 1846748Sgblack@eecs.umich.edu } 1856748Sgblack@eecs.umich.edu 1866748Sgblack@eecs.umich.edu return ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 1876748Sgblack@eecs.umich.edu } 1886748Sgblack@eecs.umich.edu 1896748Sgblack@eecs.umich.edu static uint32_t 1906748Sgblack@eecs.umich.edu spsrWriteByInstr(uint32_t spsr, uint32_t val, 1916748Sgblack@eecs.umich.edu uint8_t byteMask, bool affectState) 1926748Sgblack@eecs.umich.edu { 1936748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 1946748Sgblack@eecs.umich.edu 1956748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) 1966748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, 24); 1976748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) 1986748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 1996748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) 2006748Sgblack@eecs.umich.edu bitMask = bitMask | mask(15, 8); 2016748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) 2026748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 0); 2036748Sgblack@eecs.umich.edu 2046748Sgblack@eecs.umich.edu return ((spsr & ~bitMask) | (val & bitMask)); 2056748Sgblack@eecs.umich.edu } 2067093Sgblack@eecs.umich.edu 2077093Sgblack@eecs.umich.edu template<class XC> 2087147Sgblack@eecs.umich.edu static Addr 2097147Sgblack@eecs.umich.edu readPC(XC *xc) 2107147Sgblack@eecs.umich.edu { 2117147Sgblack@eecs.umich.edu Addr pc = xc->readPC(); 2127147Sgblack@eecs.umich.edu Addr tBit = pc & (ULL(1) << PcTBitShift); 2137147Sgblack@eecs.umich.edu if (tBit) 2147147Sgblack@eecs.umich.edu return pc + 4; 2157147Sgblack@eecs.umich.edu else 2167147Sgblack@eecs.umich.edu return pc + 8; 2177147Sgblack@eecs.umich.edu } 2187147Sgblack@eecs.umich.edu 2197148Sgblack@eecs.umich.edu // Perform an regular branch. 2207147Sgblack@eecs.umich.edu template<class XC> 2217093Sgblack@eecs.umich.edu static void 2227093Sgblack@eecs.umich.edu setNextPC(XC *xc, Addr val) 2237093Sgblack@eecs.umich.edu { 2247093Sgblack@eecs.umich.edu xc->setNextPC((xc->readNextPC() & PcModeMask) | 2257093Sgblack@eecs.umich.edu (val & ~PcModeMask)); 2267093Sgblack@eecs.umich.edu } 2277094Sgblack@eecs.umich.edu 2287148Sgblack@eecs.umich.edu // Perform an interworking branch. 2297094Sgblack@eecs.umich.edu template<class XC> 2307094Sgblack@eecs.umich.edu static void 2317148Sgblack@eecs.umich.edu setIWNextPC(XC *xc, Addr val) 2327094Sgblack@eecs.umich.edu { 2337094Sgblack@eecs.umich.edu Addr stateBits = xc->readPC() & PcModeMask; 2347094Sgblack@eecs.umich.edu Addr jBit = (ULL(1) << PcJBitShift); 2357094Sgblack@eecs.umich.edu Addr tBit = (ULL(1) << PcTBitShift); 2367094Sgblack@eecs.umich.edu bool thumbEE = (stateBits == (tBit | jBit)); 2377094Sgblack@eecs.umich.edu 2387094Sgblack@eecs.umich.edu Addr newPc = (val & ~PcModeMask); 2397094Sgblack@eecs.umich.edu if (thumbEE) { 2407094Sgblack@eecs.umich.edu if (bits(newPc, 0)) { 2417282Sgblack@eecs.umich.edu newPc = newPc & ~mask(1); 2427094Sgblack@eecs.umich.edu } else { 2437282Sgblack@eecs.umich.edu panic("Bad thumbEE interworking branch address %#x.\n", newPc); 2447094Sgblack@eecs.umich.edu } 2457094Sgblack@eecs.umich.edu } else { 2467094Sgblack@eecs.umich.edu if (bits(newPc, 0)) { 2477094Sgblack@eecs.umich.edu stateBits = tBit; 2487094Sgblack@eecs.umich.edu newPc = newPc & ~mask(1); 2497094Sgblack@eecs.umich.edu } else if (!bits(newPc, 1)) { 2507094Sgblack@eecs.umich.edu stateBits = 0; 2517094Sgblack@eecs.umich.edu } else { 2527094Sgblack@eecs.umich.edu warn("Bad interworking branch address %#x.\n", newPc); 2537094Sgblack@eecs.umich.edu } 2547094Sgblack@eecs.umich.edu } 2557094Sgblack@eecs.umich.edu newPc = newPc | stateBits; 2567094Sgblack@eecs.umich.edu xc->setNextPC(newPc); 2577094Sgblack@eecs.umich.edu } 2587148Sgblack@eecs.umich.edu 2597148Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 2607148Sgblack@eecs.umich.edu // otherwise. 2617148Sgblack@eecs.umich.edu template<class XC> 2627148Sgblack@eecs.umich.edu static void 2637148Sgblack@eecs.umich.edu setAIWNextPC(XC *xc, Addr val) 2647148Sgblack@eecs.umich.edu { 2657148Sgblack@eecs.umich.edu Addr stateBits = xc->readPC() & PcModeMask; 2667148Sgblack@eecs.umich.edu Addr jBit = (ULL(1) << PcJBitShift); 2677148Sgblack@eecs.umich.edu Addr tBit = (ULL(1) << PcTBitShift); 2687148Sgblack@eecs.umich.edu if (!jBit && !tBit) { 2697148Sgblack@eecs.umich.edu setIWNextPC(xc, val); 2707148Sgblack@eecs.umich.edu } else { 2717148Sgblack@eecs.umich.edu setNextPC(xc, val); 2727148Sgblack@eecs.umich.edu } 2737148Sgblack@eecs.umich.edu } 2747094Sgblack@eecs.umich.edu}; 2756253Sgblack@eecs.umich.edu} 2766253Sgblack@eecs.umich.edu 2776253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 278