static_inst.hh revision 7148
17093Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 147093Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_INSTS_STATICINST_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "base/trace.hh" 466253Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 476253Sgblack@eecs.umich.edu 486253Sgblack@eecs.umich.edunamespace ArmISA 496253Sgblack@eecs.umich.edu{ 507148Sgblack@eecs.umich.educlass ArmStaticInst : public StaticInst 516254Sgblack@eecs.umich.edu{ 526254Sgblack@eecs.umich.edu protected: 536255Sgblack@eecs.umich.edu int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 546255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 556255Sgblack@eecs.umich.edu int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 566255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 576254Sgblack@eecs.umich.edu 586255Sgblack@eecs.umich.edu bool shift_carry_imm(uint32_t base, uint32_t shamt, 596255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 606255Sgblack@eecs.umich.edu bool shift_carry_rs(uint32_t base, uint32_t shamt, 616255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 626254Sgblack@eecs.umich.edu 636254Sgblack@eecs.umich.edu // Constructor 647148Sgblack@eecs.umich.edu ArmStaticInst(const char *mnem, ExtMachInst _machInst, 657148Sgblack@eecs.umich.edu OpClass __opClass) 666254Sgblack@eecs.umich.edu : StaticInst(mnem, _machInst, __opClass) 676253Sgblack@eecs.umich.edu { 686254Sgblack@eecs.umich.edu } 696253Sgblack@eecs.umich.edu 706254Sgblack@eecs.umich.edu /// Print a register name for disassembly given the unique 716254Sgblack@eecs.umich.edu /// dependence tag number (FP or int). 726254Sgblack@eecs.umich.edu void printReg(std::ostream &os, int reg) const; 736262Sgblack@eecs.umich.edu void printMnemonic(std::ostream &os, 746262Sgblack@eecs.umich.edu const std::string &suffix = "", 756262Sgblack@eecs.umich.edu bool withPred = true) const; 766263Sgblack@eecs.umich.edu void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 776263Sgblack@eecs.umich.edu const std::string &prefix, const Addr addr, 786263Sgblack@eecs.umich.edu const std::string &suffix) const; 797142Sgblack@eecs.umich.edu void printShiftOperand(std::ostream &os, IntRegIndex rm, 807142Sgblack@eecs.umich.edu bool immShift, uint32_t shiftAmt, 817142Sgblack@eecs.umich.edu IntRegIndex rs, ArmShiftType type) const; 826263Sgblack@eecs.umich.edu 836253Sgblack@eecs.umich.edu 846306Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm) const; 857142Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 867142Sgblack@eecs.umich.edu IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 877142Sgblack@eecs.umich.edu IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 887142Sgblack@eecs.umich.edu uint32_t imm) const; 896264Sgblack@eecs.umich.edu 906254Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 916748Sgblack@eecs.umich.edu 926748Sgblack@eecs.umich.edu static uint32_t 936748Sgblack@eecs.umich.edu cpsrWriteByInstr(CPSR cpsr, uint32_t val, 946748Sgblack@eecs.umich.edu uint8_t byteMask, bool affectState) 956748Sgblack@eecs.umich.edu { 966748Sgblack@eecs.umich.edu bool privileged = (cpsr.mode != MODE_USER); 976748Sgblack@eecs.umich.edu 986748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 996748Sgblack@eecs.umich.edu 1006748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) { 1016748Sgblack@eecs.umich.edu unsigned lowIdx = affectState ? 24 : 27; 1026748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, lowIdx); 1036748Sgblack@eecs.umich.edu } 1046748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) { 1056748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 1066748Sgblack@eecs.umich.edu } 1076748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) { 1086748Sgblack@eecs.umich.edu unsigned highIdx = affectState ? 15 : 9; 1096748Sgblack@eecs.umich.edu unsigned lowIdx = privileged ? 8 : 9; 1106748Sgblack@eecs.umich.edu bitMask = bitMask | mask(highIdx, lowIdx); 1116748Sgblack@eecs.umich.edu } 1126748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) { 1136748Sgblack@eecs.umich.edu if (privileged) { 1146748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 6); 1156748Sgblack@eecs.umich.edu bitMask = bitMask | mask(5); 1166748Sgblack@eecs.umich.edu } 1176748Sgblack@eecs.umich.edu if (affectState) 1186748Sgblack@eecs.umich.edu bitMask = bitMask | (1 << 5); 1196748Sgblack@eecs.umich.edu } 1206748Sgblack@eecs.umich.edu 1216748Sgblack@eecs.umich.edu return ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 1226748Sgblack@eecs.umich.edu } 1236748Sgblack@eecs.umich.edu 1246748Sgblack@eecs.umich.edu static uint32_t 1256748Sgblack@eecs.umich.edu spsrWriteByInstr(uint32_t spsr, uint32_t val, 1266748Sgblack@eecs.umich.edu uint8_t byteMask, bool affectState) 1276748Sgblack@eecs.umich.edu { 1286748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 1296748Sgblack@eecs.umich.edu 1306748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) 1316748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, 24); 1326748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) 1336748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 1346748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) 1356748Sgblack@eecs.umich.edu bitMask = bitMask | mask(15, 8); 1366748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) 1376748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 0); 1386748Sgblack@eecs.umich.edu 1396748Sgblack@eecs.umich.edu return ((spsr & ~bitMask) | (val & bitMask)); 1406748Sgblack@eecs.umich.edu } 1417093Sgblack@eecs.umich.edu 1427093Sgblack@eecs.umich.edu template<class XC> 1437147Sgblack@eecs.umich.edu static Addr 1447147Sgblack@eecs.umich.edu readPC(XC *xc) 1457147Sgblack@eecs.umich.edu { 1467147Sgblack@eecs.umich.edu Addr pc = xc->readPC(); 1477147Sgblack@eecs.umich.edu Addr tBit = pc & (ULL(1) << PcTBitShift); 1487147Sgblack@eecs.umich.edu if (tBit) 1497147Sgblack@eecs.umich.edu return pc + 4; 1507147Sgblack@eecs.umich.edu else 1517147Sgblack@eecs.umich.edu return pc + 8; 1527147Sgblack@eecs.umich.edu } 1537147Sgblack@eecs.umich.edu 1547148Sgblack@eecs.umich.edu // Perform an regular branch. 1557147Sgblack@eecs.umich.edu template<class XC> 1567093Sgblack@eecs.umich.edu static void 1577093Sgblack@eecs.umich.edu setNextPC(XC *xc, Addr val) 1587093Sgblack@eecs.umich.edu { 1597093Sgblack@eecs.umich.edu xc->setNextPC((xc->readNextPC() & PcModeMask) | 1607093Sgblack@eecs.umich.edu (val & ~PcModeMask)); 1617093Sgblack@eecs.umich.edu } 1627094Sgblack@eecs.umich.edu 1637148Sgblack@eecs.umich.edu // Perform an interworking branch. 1647094Sgblack@eecs.umich.edu template<class XC> 1657094Sgblack@eecs.umich.edu static void 1667148Sgblack@eecs.umich.edu setIWNextPC(XC *xc, Addr val) 1677094Sgblack@eecs.umich.edu { 1687094Sgblack@eecs.umich.edu Addr stateBits = xc->readPC() & PcModeMask; 1697094Sgblack@eecs.umich.edu Addr jBit = (ULL(1) << PcJBitShift); 1707094Sgblack@eecs.umich.edu Addr tBit = (ULL(1) << PcTBitShift); 1717094Sgblack@eecs.umich.edu bool thumbEE = (stateBits == (tBit | jBit)); 1727094Sgblack@eecs.umich.edu 1737094Sgblack@eecs.umich.edu Addr newPc = (val & ~PcModeMask); 1747094Sgblack@eecs.umich.edu if (thumbEE) { 1757094Sgblack@eecs.umich.edu if (bits(newPc, 0)) { 1767094Sgblack@eecs.umich.edu warn("Bad thumbEE interworking branch address %#x.\n", newPc); 1777094Sgblack@eecs.umich.edu } else { 1787094Sgblack@eecs.umich.edu newPc = newPc & ~mask(1); 1797094Sgblack@eecs.umich.edu } 1807094Sgblack@eecs.umich.edu } else { 1817094Sgblack@eecs.umich.edu if (bits(newPc, 0)) { 1827094Sgblack@eecs.umich.edu stateBits = tBit; 1837094Sgblack@eecs.umich.edu newPc = newPc & ~mask(1); 1847094Sgblack@eecs.umich.edu } else if (!bits(newPc, 1)) { 1857094Sgblack@eecs.umich.edu stateBits = 0; 1867094Sgblack@eecs.umich.edu } else { 1877094Sgblack@eecs.umich.edu warn("Bad interworking branch address %#x.\n", newPc); 1887094Sgblack@eecs.umich.edu } 1897094Sgblack@eecs.umich.edu } 1907094Sgblack@eecs.umich.edu newPc = newPc | stateBits; 1917094Sgblack@eecs.umich.edu xc->setNextPC(newPc); 1927094Sgblack@eecs.umich.edu } 1937148Sgblack@eecs.umich.edu 1947148Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 1957148Sgblack@eecs.umich.edu // otherwise. 1967148Sgblack@eecs.umich.edu template<class XC> 1977148Sgblack@eecs.umich.edu static void 1987148Sgblack@eecs.umich.edu setAIWNextPC(XC *xc, Addr val) 1997148Sgblack@eecs.umich.edu { 2007148Sgblack@eecs.umich.edu Addr stateBits = xc->readPC() & PcModeMask; 2017148Sgblack@eecs.umich.edu Addr jBit = (ULL(1) << PcJBitShift); 2027148Sgblack@eecs.umich.edu Addr tBit = (ULL(1) << PcTBitShift); 2037148Sgblack@eecs.umich.edu if (!jBit && !tBit) { 2047148Sgblack@eecs.umich.edu setIWNextPC(xc, val); 2057148Sgblack@eecs.umich.edu } else { 2067148Sgblack@eecs.umich.edu setNextPC(xc, val); 2077148Sgblack@eecs.umich.edu } 2087148Sgblack@eecs.umich.edu } 2097094Sgblack@eecs.umich.edu}; 2106253Sgblack@eecs.umich.edu} 2116253Sgblack@eecs.umich.edu 2126253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 213