static_inst.hh revision 6254 
1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
30#define __ARCH_ARM_INSTS_STATICINST_HH__
31
32#include "base/trace.hh"
33#include "cpu/static_inst.hh"
34
35namespace ArmISA
36{
37class ArmStaticInst : public StaticInst
38{
39  protected:
40    // Shift Rm by an immediate value
41    int32_t
42    shift_rm_imm(uint32_t base, uint32_t shamt,
43                 uint32_t type, uint32_t cfval) const;
44
45    // Shift Rm by Rs
46    int32_t
47    shift_rm_rs(uint32_t base, uint32_t shamt,
48                uint32_t type, uint32_t cfval) const;
49
50    // Generate C for a shift by immediate
51    int32_t
52    shift_carry_imm(uint32_t base, uint32_t shamt,
53                    uint32_t type, uint32_t cfval) const;
54
55    // Generate C for a shift by Rs
56    int32_t
57    shift_carry_rs(uint32_t base, uint32_t shamt,
58                   uint32_t type, uint32_t cfval) const;
59
60    // Generate the appropriate carry bit for an addition operation
61    int32_t
62    arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
63
64    // Generate the appropriate carry bit for a subtraction operation
65    int32_t
66    arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
67
68    int32_t
69    arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
70
71    int32_t
72    arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
73
74    // Constructor
75    ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
76        : StaticInst(mnem, _machInst, __opClass)
77    {
78    }
79
80    /// Print a register name for disassembly given the unique
81    /// dependence tag number (FP or int).
82    void printReg(std::ostream &os, int reg) const;
83
84    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
85};
86}
87
88#endif //__ARCH_ARM_INSTS_STATICINST_HH__
89