static_inst.hh revision 12399
17093Sgblack@eecs.umich.edu/* 212249Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2013,2016-2017 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 147093Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_INSTS_STATICINST_HH__ 446253Sgblack@eecs.umich.edu 4510474Sandreas.hansson@arm.com#include <memory> 4610474Sandreas.hansson@arm.com 477640Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 487692SAli.Saidi@ARM.com#include "arch/arm/utility.hh" 4910037SARM gem5 Developers#include "arch/arm/system.hh" 506253Sgblack@eecs.umich.edu#include "base/trace.hh" 5112234Sgabeblack@google.com#include "cpu/exec_context.hh" 526253Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 538737Skoansin.tan@gmail.com#include "sim/byteswap.hh" 548782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 556253Sgblack@eecs.umich.edu 566253Sgblack@eecs.umich.edunamespace ArmISA 576253Sgblack@eecs.umich.edu{ 587424Sgblack@eecs.umich.edu 597148Sgblack@eecs.umich.educlass ArmStaticInst : public StaticInst 606254Sgblack@eecs.umich.edu{ 616254Sgblack@eecs.umich.edu protected: 6210037SARM gem5 Developers bool aarch64; 6310037SARM gem5 Developers uint8_t intWidth; 6410037SARM gem5 Developers 656255Sgblack@eecs.umich.edu int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 666255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 676255Sgblack@eecs.umich.edu int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 686255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 696254Sgblack@eecs.umich.edu 706255Sgblack@eecs.umich.edu bool shift_carry_imm(uint32_t base, uint32_t shamt, 716255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 726255Sgblack@eecs.umich.edu bool shift_carry_rs(uint32_t base, uint32_t shamt, 736255Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const; 746254Sgblack@eecs.umich.edu 7510037SARM gem5 Developers int64_t shiftReg64(uint64_t base, uint64_t shiftAmt, 7610037SARM gem5 Developers ArmShiftType type, uint8_t width) const; 7710037SARM gem5 Developers int64_t extendReg64(uint64_t base, ArmExtendType type, 7810037SARM gem5 Developers uint64_t shiftAmt, uint8_t width) const; 7910037SARM gem5 Developers 807193Sgblack@eecs.umich.edu template<int width> 817424Sgblack@eecs.umich.edu static inline bool 827193Sgblack@eecs.umich.edu saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) 837193Sgblack@eecs.umich.edu { 847193Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 857193Sgblack@eecs.umich.edu if (bits(midRes, width) != bits(midRes, width - 1)) { 867193Sgblack@eecs.umich.edu if (midRes > 0) 877226Sgblack@eecs.umich.edu res = (LL(1) << (width - 1)) - 1; 887193Sgblack@eecs.umich.edu else 897226Sgblack@eecs.umich.edu res = -(LL(1) << (width - 1)); 907193Sgblack@eecs.umich.edu return true; 917193Sgblack@eecs.umich.edu } else { 927193Sgblack@eecs.umich.edu res = midRes; 937193Sgblack@eecs.umich.edu return false; 947193Sgblack@eecs.umich.edu } 957193Sgblack@eecs.umich.edu } 967193Sgblack@eecs.umich.edu 977424Sgblack@eecs.umich.edu static inline bool 987226Sgblack@eecs.umich.edu satInt(int32_t &res, int64_t op, int width) 997226Sgblack@eecs.umich.edu { 1007226Sgblack@eecs.umich.edu width--; 1017226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 1027226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1037226Sgblack@eecs.umich.edu return true; 1047226Sgblack@eecs.umich.edu } else if (op < -(LL(1) << width)) { 1057226Sgblack@eecs.umich.edu res = -(LL(1) << width); 1067226Sgblack@eecs.umich.edu return true; 1077226Sgblack@eecs.umich.edu } else { 1087226Sgblack@eecs.umich.edu res = op; 1097226Sgblack@eecs.umich.edu return false; 1107226Sgblack@eecs.umich.edu } 1117226Sgblack@eecs.umich.edu } 1127226Sgblack@eecs.umich.edu 1137219Sgblack@eecs.umich.edu template<int width> 1147424Sgblack@eecs.umich.edu static inline bool 1157219Sgblack@eecs.umich.edu uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) 1167219Sgblack@eecs.umich.edu { 1177219Sgblack@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 1187226Sgblack@eecs.umich.edu if (midRes >= (LL(1) << width)) { 1197226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1207219Sgblack@eecs.umich.edu return true; 1217219Sgblack@eecs.umich.edu } else if (midRes < 0) { 1227219Sgblack@eecs.umich.edu res = 0; 1237219Sgblack@eecs.umich.edu return true; 1247219Sgblack@eecs.umich.edu } else { 1257219Sgblack@eecs.umich.edu res = midRes; 1267219Sgblack@eecs.umich.edu return false; 1277219Sgblack@eecs.umich.edu } 1287219Sgblack@eecs.umich.edu } 1297219Sgblack@eecs.umich.edu 1307424Sgblack@eecs.umich.edu static inline bool 1317226Sgblack@eecs.umich.edu uSatInt(int32_t &res, int64_t op, int width) 1327226Sgblack@eecs.umich.edu { 1337226Sgblack@eecs.umich.edu if (op >= (LL(1) << width)) { 1347226Sgblack@eecs.umich.edu res = (LL(1) << width) - 1; 1357226Sgblack@eecs.umich.edu return true; 1367226Sgblack@eecs.umich.edu } else if (op < 0) { 1377226Sgblack@eecs.umich.edu res = 0; 1387226Sgblack@eecs.umich.edu return true; 1397226Sgblack@eecs.umich.edu } else { 1407226Sgblack@eecs.umich.edu res = op; 1417226Sgblack@eecs.umich.edu return false; 1427226Sgblack@eecs.umich.edu } 1437226Sgblack@eecs.umich.edu } 1447226Sgblack@eecs.umich.edu 1456254Sgblack@eecs.umich.edu // Constructor 1467148Sgblack@eecs.umich.edu ArmStaticInst(const char *mnem, ExtMachInst _machInst, 1477148Sgblack@eecs.umich.edu OpClass __opClass) 1486254Sgblack@eecs.umich.edu : StaticInst(mnem, _machInst, __opClass) 1496253Sgblack@eecs.umich.edu { 15010037SARM gem5 Developers aarch64 = machInst.aarch64; 15110037SARM gem5 Developers if (bits(machInst, 28, 24) == 0x10) 15210037SARM gem5 Developers intWidth = 64; // Force 64-bit width for ADR/ADRP 15310037SARM gem5 Developers else 15410037SARM gem5 Developers intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32; 1556254Sgblack@eecs.umich.edu } 1566253Sgblack@eecs.umich.edu 1576254Sgblack@eecs.umich.edu /// Print a register name for disassembly given the unique 1586254Sgblack@eecs.umich.edu /// dependence tag number (FP or int). 15912104Snathanael.premillieu@arm.com void printIntReg(std::ostream &os, RegIndex reg_idx) const; 16012104Snathanael.premillieu@arm.com void printFloatReg(std::ostream &os, RegIndex reg_idx) const; 16112109SRekai.GonzalezAlberquilla@arm.com void printVecReg(std::ostream &os, RegIndex reg_idx) const; 16212104Snathanael.premillieu@arm.com void printCCReg(std::ostream &os, RegIndex reg_idx) const; 16312104Snathanael.premillieu@arm.com void printMiscReg(std::ostream &os, RegIndex reg_idx) const; 1646262Sgblack@eecs.umich.edu void printMnemonic(std::ostream &os, 1656262Sgblack@eecs.umich.edu const std::string &suffix = "", 16610037SARM gem5 Developers bool withPred = true, 16710037SARM gem5 Developers bool withCond64 = false, 16810037SARM gem5 Developers ConditionCode cond64 = COND_UC) const; 16910037SARM gem5 Developers void printTarget(std::ostream &os, Addr target, 17010037SARM gem5 Developers const SymbolTable *symtab) const; 17110037SARM gem5 Developers void printCondition(std::ostream &os, unsigned code, 17210037SARM gem5 Developers bool noImplicit=false) const; 1736263Sgblack@eecs.umich.edu void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 1746263Sgblack@eecs.umich.edu const std::string &prefix, const Addr addr, 1756263Sgblack@eecs.umich.edu const std::string &suffix) const; 1767142Sgblack@eecs.umich.edu void printShiftOperand(std::ostream &os, IntRegIndex rm, 1777142Sgblack@eecs.umich.edu bool immShift, uint32_t shiftAmt, 1787142Sgblack@eecs.umich.edu IntRegIndex rs, ArmShiftType type) const; 17910037SARM gem5 Developers void printExtendOperand(bool firstOperand, std::ostream &os, 18010037SARM gem5 Developers IntRegIndex rm, ArmExtendType type, 18110037SARM gem5 Developers int64_t shiftAmt) const; 1826263Sgblack@eecs.umich.edu 1836253Sgblack@eecs.umich.edu 1846306Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm) const; 1857142Sgblack@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 1867142Sgblack@eecs.umich.edu IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 1877142Sgblack@eecs.umich.edu IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 18811371Snathanael.premillieu@arm.com uint64_t imm) const; 1896264Sgblack@eecs.umich.edu 1907720Sgblack@eecs.umich.edu void 1917720Sgblack@eecs.umich.edu advancePC(PCState &pcState) const 1927720Sgblack@eecs.umich.edu { 1937720Sgblack@eecs.umich.edu pcState.advance(); 1947720Sgblack@eecs.umich.edu } 1957720Sgblack@eecs.umich.edu 1966254Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1976748Sgblack@eecs.umich.edu 1987424Sgblack@eecs.umich.edu static inline uint32_t 19910037SARM gem5 Developers cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, 20010037SARM gem5 Developers uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc) 2016748Sgblack@eecs.umich.edu { 20210037SARM gem5 Developers bool privileged = (cpsr.mode != MODE_USER); 20310037SARM gem5 Developers bool haveVirt = ArmSystem::haveVirtualization(tc); 20410037SARM gem5 Developers bool haveSecurity = ArmSystem::haveSecurity(tc); 20510037SARM gem5 Developers bool isSecure = inSecureState(scr, cpsr) || !haveSecurity; 2066748Sgblack@eecs.umich.edu 2076748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 2086748Sgblack@eecs.umich.edu 2096748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) { 2106748Sgblack@eecs.umich.edu unsigned lowIdx = affectState ? 24 : 27; 2116748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, lowIdx); 2126748Sgblack@eecs.umich.edu } 2136748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) { 2146748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 2156748Sgblack@eecs.umich.edu } 2166748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) { 2176748Sgblack@eecs.umich.edu unsigned highIdx = affectState ? 15 : 9; 21810037SARM gem5 Developers unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt)) 21910037SARM gem5 Developers ? 8 : 9; 2206748Sgblack@eecs.umich.edu bitMask = bitMask | mask(highIdx, lowIdx); 2216748Sgblack@eecs.umich.edu } 2226748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) { 2236748Sgblack@eecs.umich.edu if (privileged) { 22410037SARM gem5 Developers bitMask |= 1 << 7; 22510037SARM gem5 Developers if ( (!nmfi || !((val >> 6) & 0x1)) && 22610037SARM gem5 Developers (isSecure || scr.fw || haveVirt) ) { 22710037SARM gem5 Developers bitMask |= 1 << 6; 22810037SARM gem5 Developers } 22910037SARM gem5 Developers // Now check the new mode is allowed 23010037SARM gem5 Developers OperatingMode newMode = (OperatingMode) (val & mask(5)); 23110037SARM gem5 Developers OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode; 23210037SARM gem5 Developers if (!badMode(newMode)) { 23310037SARM gem5 Developers bool validModeChange = true; 23410037SARM gem5 Developers // Check for attempts to enter modes only permitted in 23510037SARM gem5 Developers // Secure state from Non-secure state. These are Monitor 23610037SARM gem5 Developers // mode ('10110'), and FIQ mode ('10001') if the Security 23710037SARM gem5 Developers // Extensions have reserved it. 23810037SARM gem5 Developers if (!isSecure && newMode == MODE_MON) 23910037SARM gem5 Developers validModeChange = false; 24010037SARM gem5 Developers if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1') 24110037SARM gem5 Developers validModeChange = false; 24210037SARM gem5 Developers // There is no Hyp mode ('11010') in Secure state, so that 24310037SARM gem5 Developers // is UNPREDICTABLE 24410037SARM gem5 Developers if (scr.ns == '0' && newMode == MODE_HYP) 24510037SARM gem5 Developers validModeChange = false; 24610037SARM gem5 Developers // Cannot move into Hyp mode directly from a Non-secure 24710037SARM gem5 Developers // PL1 mode 24810037SARM gem5 Developers if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP) 24910037SARM gem5 Developers validModeChange = false; 25010037SARM gem5 Developers // Cannot move out of Hyp mode with this function except 25110037SARM gem5 Developers // on an exception return 25210037SARM gem5 Developers if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState) 25310037SARM gem5 Developers validModeChange = false; 25410037SARM gem5 Developers // Must not change to 64 bit when running in 32 bit mode 25510037SARM gem5 Developers if (!opModeIs64(oldMode) && opModeIs64(newMode)) 25610037SARM gem5 Developers validModeChange = false; 25710037SARM gem5 Developers 25810037SARM gem5 Developers // If we passed all of the above then set the bit mask to 25910037SARM gem5 Developers // copy the mode accross 26010037SARM gem5 Developers if (validModeChange) { 26110037SARM gem5 Developers bitMask = bitMask | mask(5); 26210037SARM gem5 Developers } else { 26310037SARM gem5 Developers warn_once("Illegal change to CPSR mode attempted\n"); 26410037SARM gem5 Developers } 2657317Sgblack@eecs.umich.edu } else { 2667317Sgblack@eecs.umich.edu warn_once("Ignoring write of bad mode to CPSR.\n"); 2677317Sgblack@eecs.umich.edu } 2686748Sgblack@eecs.umich.edu } 2696748Sgblack@eecs.umich.edu if (affectState) 2706748Sgblack@eecs.umich.edu bitMask = bitMask | (1 << 5); 2716748Sgblack@eecs.umich.edu } 2726748Sgblack@eecs.umich.edu 27310037SARM gem5 Developers return ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 2746748Sgblack@eecs.umich.edu } 2756748Sgblack@eecs.umich.edu 2767424Sgblack@eecs.umich.edu static inline uint32_t 2776748Sgblack@eecs.umich.edu spsrWriteByInstr(uint32_t spsr, uint32_t val, 2786748Sgblack@eecs.umich.edu uint8_t byteMask, bool affectState) 2796748Sgblack@eecs.umich.edu { 2806748Sgblack@eecs.umich.edu uint32_t bitMask = 0; 2816748Sgblack@eecs.umich.edu 2826748Sgblack@eecs.umich.edu if (bits(byteMask, 3)) 2836748Sgblack@eecs.umich.edu bitMask = bitMask | mask(31, 24); 2846748Sgblack@eecs.umich.edu if (bits(byteMask, 2)) 2856748Sgblack@eecs.umich.edu bitMask = bitMask | mask(19, 16); 2866748Sgblack@eecs.umich.edu if (bits(byteMask, 1)) 2876748Sgblack@eecs.umich.edu bitMask = bitMask | mask(15, 8); 2886748Sgblack@eecs.umich.edu if (bits(byteMask, 0)) 2896748Sgblack@eecs.umich.edu bitMask = bitMask | mask(7, 0); 2906748Sgblack@eecs.umich.edu 2916748Sgblack@eecs.umich.edu return ((spsr & ~bitMask) | (val & bitMask)); 2926748Sgblack@eecs.umich.edu } 2937093Sgblack@eecs.umich.edu 2947424Sgblack@eecs.umich.edu static inline Addr 29512234Sgabeblack@google.com readPC(ExecContext *xc) 2967147Sgblack@eecs.umich.edu { 2977720Sgblack@eecs.umich.edu return xc->pcState().instPC(); 2987147Sgblack@eecs.umich.edu } 2997147Sgblack@eecs.umich.edu 3007424Sgblack@eecs.umich.edu static inline void 30112234Sgabeblack@google.com setNextPC(ExecContext *xc, Addr val) 3027093Sgblack@eecs.umich.edu { 3037720Sgblack@eecs.umich.edu PCState pc = xc->pcState(); 3047720Sgblack@eecs.umich.edu pc.instNPC(val); 3057720Sgblack@eecs.umich.edu xc->pcState(pc); 3067093Sgblack@eecs.umich.edu } 3077094Sgblack@eecs.umich.edu 3087296Sgblack@eecs.umich.edu template<class T> 3097424Sgblack@eecs.umich.edu static inline T 3107296Sgblack@eecs.umich.edu cSwap(T val, bool big) 3117296Sgblack@eecs.umich.edu { 3127296Sgblack@eecs.umich.edu if (big) { 3137296Sgblack@eecs.umich.edu return gtobe(val); 3147296Sgblack@eecs.umich.edu } else { 3157296Sgblack@eecs.umich.edu return gtole(val); 3167296Sgblack@eecs.umich.edu } 3177296Sgblack@eecs.umich.edu } 3187296Sgblack@eecs.umich.edu 3197639Sgblack@eecs.umich.edu template<class T, class E> 3207639Sgblack@eecs.umich.edu static inline T 3217639Sgblack@eecs.umich.edu cSwap(T val, bool big) 3227639Sgblack@eecs.umich.edu { 3237639Sgblack@eecs.umich.edu const unsigned count = sizeof(T) / sizeof(E); 3247639Sgblack@eecs.umich.edu union { 3257639Sgblack@eecs.umich.edu T tVal; 3267639Sgblack@eecs.umich.edu E eVals[count]; 3277639Sgblack@eecs.umich.edu } conv; 3287639Sgblack@eecs.umich.edu conv.tVal = htog(val); 3297639Sgblack@eecs.umich.edu if (big) { 3307639Sgblack@eecs.umich.edu for (unsigned i = 0; i < count; i++) { 3317639Sgblack@eecs.umich.edu conv.eVals[i] = gtobe(conv.eVals[i]); 3327639Sgblack@eecs.umich.edu } 3337639Sgblack@eecs.umich.edu } else { 3347639Sgblack@eecs.umich.edu for (unsigned i = 0; i < count; i++) { 3357639Sgblack@eecs.umich.edu conv.eVals[i] = gtole(conv.eVals[i]); 3367639Sgblack@eecs.umich.edu } 3377639Sgblack@eecs.umich.edu } 3387639Sgblack@eecs.umich.edu return gtoh(conv.tVal); 3397639Sgblack@eecs.umich.edu } 3407639Sgblack@eecs.umich.edu 3417148Sgblack@eecs.umich.edu // Perform an interworking branch. 3427424Sgblack@eecs.umich.edu static inline void 34312234Sgabeblack@google.com setIWNextPC(ExecContext *xc, Addr val) 3447094Sgblack@eecs.umich.edu { 3457720Sgblack@eecs.umich.edu PCState pc = xc->pcState(); 3467720Sgblack@eecs.umich.edu pc.instIWNPC(val); 3477720Sgblack@eecs.umich.edu xc->pcState(pc); 3487094Sgblack@eecs.umich.edu } 3497148Sgblack@eecs.umich.edu 3507148Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 3517148Sgblack@eecs.umich.edu // otherwise. 3527424Sgblack@eecs.umich.edu static inline void 35312234Sgabeblack@google.com setAIWNextPC(ExecContext *xc, Addr val) 3547148Sgblack@eecs.umich.edu { 3557720Sgblack@eecs.umich.edu PCState pc = xc->pcState(); 3567720Sgblack@eecs.umich.edu pc.instAIWNPC(val); 3577720Sgblack@eecs.umich.edu xc->pcState(pc); 3587148Sgblack@eecs.umich.edu } 3597640Sgblack@eecs.umich.edu 3607640Sgblack@eecs.umich.edu inline Fault 3617640Sgblack@eecs.umich.edu disabledFault() const 3627640Sgblack@eecs.umich.edu { 36310474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 36410474Sandreas.hansson@arm.com mnemonic, true); 3657640Sgblack@eecs.umich.edu } 36610037SARM gem5 Developers 36711513Sandreas.sandberg@arm.com /** 36811513Sandreas.sandberg@arm.com * Trap an access to Advanced SIMD or FP registers due to access 36911513Sandreas.sandberg@arm.com * control bits. 37011513Sandreas.sandberg@arm.com * 37111513Sandreas.sandberg@arm.com * See aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap in the 37211513Sandreas.sandberg@arm.com * ARM ARM psueodcode library. 37311513Sandreas.sandberg@arm.com * 37411513Sandreas.sandberg@arm.com * @param el Target EL for the trap 37511513Sandreas.sandberg@arm.com */ 37611513Sandreas.sandberg@arm.com Fault advSIMDFPAccessTrap64(ExceptionLevel el) const; 37711513Sandreas.sandberg@arm.com 37811513Sandreas.sandberg@arm.com 37911513Sandreas.sandberg@arm.com /** 38011513Sandreas.sandberg@arm.com * Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. 38111513Sandreas.sandberg@arm.com * 38211513Sandreas.sandberg@arm.com * See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap in the 38311513Sandreas.sandberg@arm.com * ARM ARM psueodcode library. 38411513Sandreas.sandberg@arm.com */ 38511513Sandreas.sandberg@arm.com Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const; 38611513Sandreas.sandberg@arm.com 38711513Sandreas.sandberg@arm.com /** 38811513Sandreas.sandberg@arm.com * Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and 38911513Sandreas.sandberg@arm.com * CPTR_EL3. 39011513Sandreas.sandberg@arm.com * 39111513Sandreas.sandberg@arm.com * See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled in the 39211513Sandreas.sandberg@arm.com * ARM ARM psueodcode library. 39311513Sandreas.sandberg@arm.com */ 39411513Sandreas.sandberg@arm.com Fault checkFPAdvSIMDEnabled64(ThreadContext *tc, 39511513Sandreas.sandberg@arm.com CPSR cpsr, CPACR cpacr) const; 39611513Sandreas.sandberg@arm.com 39711513Sandreas.sandberg@arm.com /** 39811513Sandreas.sandberg@arm.com * Check if a VFP/SIMD access from aarch32 should be allowed. 39911513Sandreas.sandberg@arm.com * 40011513Sandreas.sandberg@arm.com * See aarch32/exceptions/traps/AArch32.CheckAdvSIMDOrFPEnabled in the 40111513Sandreas.sandberg@arm.com * ARM ARM psueodcode library. 40211513Sandreas.sandberg@arm.com */ 40311513Sandreas.sandberg@arm.com Fault checkAdvSIMDOrFPEnabled32(ThreadContext *tc, 40411513Sandreas.sandberg@arm.com CPSR cpsr, CPACR cpacr, 40511513Sandreas.sandberg@arm.com NSACR nsacr, FPEXC fpexc, 40611513Sandreas.sandberg@arm.com bool fpexc_check, bool advsimd) const; 40711513Sandreas.sandberg@arm.com 40811514Sandreas.sandberg@arm.com /** 40911514Sandreas.sandberg@arm.com * Get the new PSTATE from a SPSR register in preparation for an 41011514Sandreas.sandberg@arm.com * exception return. 41111514Sandreas.sandberg@arm.com * 41211514Sandreas.sandberg@arm.com * See shared/functions/system/SetPSTATEFromPSR in the ARM ARM 41311514Sandreas.sandberg@arm.com * psueodcode library. 41411514Sandreas.sandberg@arm.com */ 41511514Sandreas.sandberg@arm.com CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const; 41611514Sandreas.sandberg@arm.com 41710037SARM gem5 Developers public: 41810037SARM gem5 Developers virtual void 41910037SARM gem5 Developers annotateFault(ArmFault *fault) {} 42012249Sgiacomo.travaglini@arm.com 42112249Sgiacomo.travaglini@arm.com uint8_t 42212249Sgiacomo.travaglini@arm.com getIntWidth() const 42312249Sgiacomo.travaglini@arm.com { 42412249Sgiacomo.travaglini@arm.com return intWidth; 42512249Sgiacomo.travaglini@arm.com } 42612399Sgiacomo.travaglini@arm.com 42712399Sgiacomo.travaglini@arm.com /** Returns the byte size of current instruction */ 42812399Sgiacomo.travaglini@arm.com ssize_t 42912399Sgiacomo.travaglini@arm.com instSize() const 43012399Sgiacomo.travaglini@arm.com { 43112399Sgiacomo.travaglini@arm.com return (!machInst.thumb || machInst.bigThumb) ? 4 : 2; 43212399Sgiacomo.travaglini@arm.com } 43312399Sgiacomo.travaglini@arm.com 43412399Sgiacomo.travaglini@arm.com /** 43512399Sgiacomo.travaglini@arm.com * Returns the real encoding of the instruction: 43612399Sgiacomo.travaglini@arm.com * the machInst field is in fact always 64 bit wide and 43712399Sgiacomo.travaglini@arm.com * contains some instruction metadata, which means it differs 43812399Sgiacomo.travaglini@arm.com * from the real opcode. 43912399Sgiacomo.travaglini@arm.com */ 44012399Sgiacomo.travaglini@arm.com MachInst 44112399Sgiacomo.travaglini@arm.com encoding() const 44212399Sgiacomo.travaglini@arm.com { 44312399Sgiacomo.travaglini@arm.com return static_cast<MachInst>(mask(instSize() * 8)); 44412399Sgiacomo.travaglini@arm.com } 4457094Sgblack@eecs.umich.edu}; 4466253Sgblack@eecs.umich.edu} 4476253Sgblack@eecs.umich.edu 4486253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 449