static_inst.cc revision 9920:028e4da64b42 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Stephen Hines
42 */
43
44#include "arch/arm/insts/static_inst.hh"
45#include "arch/arm/faults.hh"
46#include "base/loader/symtab.hh"
47#include "base/condcodes.hh"
48#include "base/cprintf.hh"
49#include "cpu/reg_class.hh"
50
51namespace ArmISA
52{
53// Shift Rm by an immediate value
54int32_t
55ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
56                                uint32_t type, uint32_t cfval) const
57{
58    assert(shamt < 32);
59    ArmShiftType shiftType;
60    shiftType = (ArmShiftType)type;
61
62    switch (shiftType)
63    {
64      case LSL:
65        return base << shamt;
66      case LSR:
67        if (shamt == 0)
68            return 0;
69        else
70            return base >> shamt;
71      case ASR:
72        if (shamt == 0)
73            return (base >> 31) | -((base & (1 << 31)) >> 31);
74        else
75            return (base >> shamt) | -((base & (1 << 31)) >> shamt);
76      case ROR:
77        if (shamt == 0)
78            return (cfval << 31) | (base >> 1); // RRX
79        else
80            return (base << (32 - shamt)) | (base >> shamt);
81      default:
82        ccprintf(std::cerr, "Unhandled shift type\n");
83        exit(1);
84        break;
85    }
86    return 0;
87}
88
89// Shift Rm by Rs
90int32_t
91ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
92                               uint32_t type, uint32_t cfval) const
93{
94    enum ArmShiftType shiftType;
95    shiftType = (enum ArmShiftType) type;
96
97    switch (shiftType)
98    {
99      case LSL:
100        if (shamt >= 32)
101            return 0;
102        else
103            return base << shamt;
104      case LSR:
105        if (shamt >= 32)
106            return 0;
107        else
108            return base >> shamt;
109      case ASR:
110        if (shamt >= 32)
111            return (base >> 31) | -((base & (1 << 31)) >> 31);
112        else
113            return (base >> shamt) | -((base & (1 << 31)) >> shamt);
114      case ROR:
115        shamt = shamt & 0x1f;
116        if (shamt == 0)
117            return base;
118        else
119            return (base << (32 - shamt)) | (base >> shamt);
120      default:
121        ccprintf(std::cerr, "Unhandled shift type\n");
122        exit(1);
123        break;
124    }
125    return 0;
126}
127
128
129// Generate C for a shift by immediate
130bool
131ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
132                                   uint32_t type, uint32_t cfval) const
133{
134    enum ArmShiftType shiftType;
135    shiftType = (enum ArmShiftType) type;
136
137    switch (shiftType)
138    {
139      case LSL:
140        if (shamt == 0)
141            return cfval;
142        else
143            return (base >> (32 - shamt)) & 1;
144      case LSR:
145        if (shamt == 0)
146            return (base >> 31);
147        else
148            return (base >> (shamt - 1)) & 1;
149      case ASR:
150        if (shamt == 0)
151            return (base >> 31);
152        else
153            return (base >> (shamt - 1)) & 1;
154      case ROR:
155        shamt = shamt & 0x1f;
156        if (shamt == 0)
157            return (base & 1); // RRX
158        else
159            return (base >> (shamt - 1)) & 1;
160      default:
161        ccprintf(std::cerr, "Unhandled shift type\n");
162        exit(1);
163        break;
164    }
165    return 0;
166}
167
168
169// Generate C for a shift by Rs
170bool
171ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
172                                  uint32_t type, uint32_t cfval) const
173{
174    enum ArmShiftType shiftType;
175    shiftType = (enum ArmShiftType) type;
176
177    if (shamt == 0)
178        return cfval;
179
180    switch (shiftType)
181    {
182      case LSL:
183        if (shamt > 32)
184            return 0;
185        else
186            return (base >> (32 - shamt)) & 1;
187      case LSR:
188        if (shamt > 32)
189            return 0;
190        else
191            return (base >> (shamt - 1)) & 1;
192      case ASR:
193        if (shamt > 32)
194            shamt = 32;
195        return (base >> (shamt - 1)) & 1;
196      case ROR:
197        shamt = shamt & 0x1f;
198        if (shamt == 0)
199            shamt = 32;
200        return (base >> (shamt - 1)) & 1;
201      default:
202        ccprintf(std::cerr, "Unhandled shift type\n");
203        exit(1);
204        break;
205    }
206    return 0;
207}
208
209
210void
211ArmStaticInst::printReg(std::ostream &os, int reg) const
212{
213    RegIndex rel_reg;
214
215    switch (regIdxToClass(reg, &rel_reg)) {
216      case IntRegClass:
217        switch (rel_reg) {
218          case PCReg:
219            ccprintf(os, "pc");
220            break;
221          case StackPointerReg:
222            ccprintf(os, "sp");
223            break;
224          case FramePointerReg:
225            ccprintf(os, "fp");
226            break;
227          case ReturnAddressReg:
228            ccprintf(os, "lr");
229            break;
230          default:
231            ccprintf(os, "r%d", reg);
232            break;
233        }
234        break;
235      case FloatRegClass:
236        ccprintf(os, "f%d", rel_reg);
237        break;
238      case MiscRegClass:
239        assert(rel_reg < NUM_MISCREGS);
240        ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
241        break;
242      case CCRegClass:
243        panic("printReg: CCRegClass but ARM has no CC regs\n");
244    }
245}
246
247void
248ArmStaticInst::printMnemonic(std::ostream &os,
249                             const std::string &suffix,
250                             bool withPred) const
251{
252    os << "  " << mnemonic;
253    if (withPred) {
254        unsigned condCode = machInst.condCode;
255        switch (condCode) {
256          case COND_EQ:
257            os << "eq";
258            break;
259          case COND_NE:
260            os << "ne";
261            break;
262          case COND_CS:
263            os << "cs";
264            break;
265          case COND_CC:
266            os << "cc";
267            break;
268          case COND_MI:
269            os << "mi";
270            break;
271          case COND_PL:
272            os << "pl";
273            break;
274          case COND_VS:
275            os << "vs";
276            break;
277          case COND_VC:
278            os << "vc";
279            break;
280          case COND_HI:
281            os << "hi";
282            break;
283          case COND_LS:
284            os << "ls";
285            break;
286          case COND_GE:
287            os << "ge";
288            break;
289          case COND_LT:
290            os << "lt";
291            break;
292          case COND_GT:
293            os << "gt";
294            break;
295          case COND_LE:
296            os << "le";
297            break;
298          case COND_AL:
299            // This one is implicit.
300            break;
301          case COND_UC:
302            // Unconditional.
303            break;
304          default:
305            panic("Unrecognized condition code %d.\n", condCode);
306        }
307        os << suffix;
308        if (machInst.bigThumb)
309            os << ".w";
310        os << "   ";
311    }
312}
313
314void
315ArmStaticInst::printMemSymbol(std::ostream &os,
316                              const SymbolTable *symtab,
317                              const std::string &prefix,
318                              const Addr addr,
319                              const std::string &suffix) const
320{
321    Addr symbolAddr;
322    std::string symbol;
323    if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) {
324        ccprintf(os, "%s%s", prefix, symbol);
325        if (symbolAddr != addr)
326            ccprintf(os, "+%d", addr - symbolAddr);
327        ccprintf(os, suffix);
328    }
329}
330
331void
332ArmStaticInst::printShiftOperand(std::ostream &os,
333                                     IntRegIndex rm,
334                                     bool immShift,
335                                     uint32_t shiftAmt,
336                                     IntRegIndex rs,
337                                     ArmShiftType type) const
338{
339    bool firstOp = false;
340
341    if (rm != INTREG_ZERO) {
342        printReg(os, rm);
343    }
344
345    bool done = false;
346
347    if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
348        shiftAmt = 32;
349
350    switch (type) {
351      case LSL:
352        if (immShift && shiftAmt == 0) {
353            done = true;
354            break;
355        }
356        if (!firstOp)
357            os << ", ";
358        os << "LSL";
359        break;
360      case LSR:
361        if (!firstOp)
362            os << ", ";
363        os << "LSR";
364        break;
365      case ASR:
366        if (!firstOp)
367            os << ", ";
368        os << "ASR";
369        break;
370      case ROR:
371        if (immShift && shiftAmt == 0) {
372            if (!firstOp)
373                os << ", ";
374            os << "RRX";
375            done = true;
376            break;
377        }
378        if (!firstOp)
379            os << ", ";
380        os << "ROR";
381        break;
382      default:
383        panic("Tried to disassemble unrecognized shift type.\n");
384    }
385    if (!done) {
386        if (!firstOp)
387            os << " ";
388        if (immShift)
389            os << "#" << shiftAmt;
390        else
391            printReg(os, rs);
392    }
393}
394
395void
396ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
397        bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
398        IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
399        ArmShiftType type, uint32_t imm) const
400{
401    printMnemonic(os, s ? "s" : "");
402    bool firstOp = true;
403
404    // Destination
405    if (rd != INTREG_ZERO) {
406        firstOp = false;
407        printReg(os, rd);
408    }
409
410    // Source 1.
411    if (rn != INTREG_ZERO) {
412        if (!firstOp)
413            os << ", ";
414        firstOp = false;
415        printReg(os, rn);
416    }
417
418    if (!firstOp)
419        os << ", ";
420    if (withImm) {
421        ccprintf(os, "#%d", imm);
422    } else {
423        printShiftOperand(os, rm, immShift, shiftAmt, rs, type);
424    }
425}
426
427std::string
428ArmStaticInst::generateDisassembly(Addr pc,
429                                   const SymbolTable *symtab) const
430{
431    std::stringstream ss;
432    printMnemonic(ss);
433    return ss.str();
434}
435}
436