static_inst.cc revision 12104:edd63f9c6184 
1/*
2 * Copyright (c) 2010-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Stephen Hines
42 */
43
44#include "arch/arm/insts/static_inst.hh"
45
46#include "arch/arm/faults.hh"
47#include "base/condcodes.hh"
48#include "base/cprintf.hh"
49#include "base/loader/symtab.hh"
50#include "cpu/reg_class.hh"
51
52namespace ArmISA
53{
54// Shift Rm by an immediate value
55int32_t
56ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
57                                uint32_t type, uint32_t cfval) const
58{
59    assert(shamt < 32);
60    ArmShiftType shiftType;
61    shiftType = (ArmShiftType)type;
62
63    switch (shiftType)
64    {
65      case LSL:
66        return base << shamt;
67      case LSR:
68        if (shamt == 0)
69            return 0;
70        else
71            return base >> shamt;
72      case ASR:
73        if (shamt == 0)
74            return (base >> 31) | -((base & (1 << 31)) >> 31);
75        else
76            return (base >> shamt) | -((base & (1 << 31)) >> shamt);
77      case ROR:
78        if (shamt == 0)
79            return (cfval << 31) | (base >> 1); // RRX
80        else
81            return (base << (32 - shamt)) | (base >> shamt);
82      default:
83        ccprintf(std::cerr, "Unhandled shift type\n");
84        exit(1);
85        break;
86    }
87    return 0;
88}
89
90int64_t
91ArmStaticInst::shiftReg64(uint64_t base, uint64_t shiftAmt,
92                          ArmShiftType type, uint8_t width) const
93{
94    shiftAmt = shiftAmt % width;
95    ArmShiftType shiftType;
96    shiftType = (ArmShiftType)type;
97
98    switch (shiftType)
99    {
100      case LSL:
101        return base << shiftAmt;
102      case LSR:
103        if (shiftAmt == 0)
104            return base;
105        else
106            return (base & mask(width)) >> shiftAmt;
107      case ASR:
108        if (shiftAmt == 0) {
109            return base;
110        } else {
111            int sign_bit = bits(base, intWidth - 1);
112            base >>= shiftAmt;
113            base = sign_bit ? (base | ~mask(intWidth - shiftAmt)) : base;
114            return base & mask(intWidth);
115        }
116      case ROR:
117        if (shiftAmt == 0)
118            return base;
119        else
120            return (base << (width - shiftAmt)) | (base >> shiftAmt);
121      default:
122        ccprintf(std::cerr, "Unhandled shift type\n");
123        exit(1);
124        break;
125    }
126    return 0;
127}
128
129int64_t
130ArmStaticInst::extendReg64(uint64_t base, ArmExtendType type,
131                           uint64_t shiftAmt, uint8_t width) const
132{
133    bool sign_extend = false;
134    int len = 0;
135    switch (type) {
136      case UXTB:
137        len = 8;
138        break;
139      case UXTH:
140        len = 16;
141        break;
142      case UXTW:
143        len = 32;
144        break;
145      case UXTX:
146        len = 64;
147        break;
148      case SXTB:
149        len = 8;
150        sign_extend = true;
151        break;
152      case SXTH:
153        len = 16;
154        sign_extend = true;
155        break;
156      case SXTW:
157        len = 32;
158        sign_extend = true;
159        break;
160      case SXTX:
161        len = 64;
162        sign_extend = true;
163        break;
164    }
165    len = len <= width - shiftAmt ? len : width - shiftAmt;
166    uint64_t tmp = (uint64_t) bits(base, len - 1, 0) << shiftAmt;
167    if (sign_extend) {
168        int sign_bit = bits(tmp, len + shiftAmt - 1);
169        tmp = sign_bit ? (tmp | ~mask(len + shiftAmt)) : tmp;
170    }
171    return tmp & mask(width);
172}
173
174// Shift Rm by Rs
175int32_t
176ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
177                               uint32_t type, uint32_t cfval) const
178{
179    enum ArmShiftType shiftType;
180    shiftType = (enum ArmShiftType) type;
181
182    switch (shiftType)
183    {
184      case LSL:
185        if (shamt >= 32)
186            return 0;
187        else
188            return base << shamt;
189      case LSR:
190        if (shamt >= 32)
191            return 0;
192        else
193            return base >> shamt;
194      case ASR:
195        if (shamt >= 32)
196            return (base >> 31) | -((base & (1 << 31)) >> 31);
197        else
198            return (base >> shamt) | -((base & (1 << 31)) >> shamt);
199      case ROR:
200        shamt = shamt & 0x1f;
201        if (shamt == 0)
202            return base;
203        else
204            return (base << (32 - shamt)) | (base >> shamt);
205      default:
206        ccprintf(std::cerr, "Unhandled shift type\n");
207        exit(1);
208        break;
209    }
210    return 0;
211}
212
213
214// Generate C for a shift by immediate
215bool
216ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
217                                   uint32_t type, uint32_t cfval) const
218{
219    enum ArmShiftType shiftType;
220    shiftType = (enum ArmShiftType) type;
221
222    switch (shiftType)
223    {
224      case LSL:
225        if (shamt == 0)
226            return cfval;
227        else
228            return (base >> (32 - shamt)) & 1;
229      case LSR:
230        if (shamt == 0)
231            return (base >> 31);
232        else
233            return (base >> (shamt - 1)) & 1;
234      case ASR:
235        if (shamt == 0)
236            return (base >> 31);
237        else
238            return (base >> (shamt - 1)) & 1;
239      case ROR:
240        shamt = shamt & 0x1f;
241        if (shamt == 0)
242            return (base & 1); // RRX
243        else
244            return (base >> (shamt - 1)) & 1;
245      default:
246        ccprintf(std::cerr, "Unhandled shift type\n");
247        exit(1);
248        break;
249    }
250    return 0;
251}
252
253
254// Generate C for a shift by Rs
255bool
256ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
257                                  uint32_t type, uint32_t cfval) const
258{
259    enum ArmShiftType shiftType;
260    shiftType = (enum ArmShiftType) type;
261
262    if (shamt == 0)
263        return cfval;
264
265    switch (shiftType)
266    {
267      case LSL:
268        if (shamt > 32)
269            return 0;
270        else
271            return (base >> (32 - shamt)) & 1;
272      case LSR:
273        if (shamt > 32)
274            return 0;
275        else
276            return (base >> (shamt - 1)) & 1;
277      case ASR:
278        if (shamt > 32)
279            shamt = 32;
280        return (base >> (shamt - 1)) & 1;
281      case ROR:
282        shamt = shamt & 0x1f;
283        if (shamt == 0)
284            shamt = 32;
285        return (base >> (shamt - 1)) & 1;
286      default:
287        ccprintf(std::cerr, "Unhandled shift type\n");
288        exit(1);
289        break;
290    }
291    return 0;
292}
293
294void
295ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx) const
296{
297    if (aarch64) {
298        if (reg_idx == INTREG_UREG0)
299            ccprintf(os, "ureg0");
300        else if (reg_idx == INTREG_SPX)
301            ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
302        else if (reg_idx == INTREG_X31)
303            ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
304        else
305            ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg_idx);
306    } else {
307        switch (reg_idx) {
308          case PCReg:
309            ccprintf(os, "pc");
310            break;
311          case StackPointerReg:
312            ccprintf(os, "sp");
313            break;
314          case FramePointerReg:
315             ccprintf(os, "fp");
316             break;
317          case ReturnAddressReg:
318             ccprintf(os, "lr");
319             break;
320          default:
321             ccprintf(os, "r%d", reg_idx);
322             break;
323        }
324    }
325}
326
327void
328ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
329{
330    ccprintf(os, "f%d", reg_idx);
331}
332
333void
334ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
335{
336    ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
337}
338
339void
340ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
341{
342    assert(reg_idx < NUM_MISCREGS);
343    ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);
344}
345
346void
347ArmStaticInst::printMnemonic(std::ostream &os,
348                             const std::string &suffix,
349                             bool withPred,
350                             bool withCond64,
351                             ConditionCode cond64) const
352{
353    os << "  " << mnemonic;
354    if (withPred && !aarch64) {
355        printCondition(os, machInst.condCode);
356        os << suffix;
357    } else if (withCond64) {
358        os << ".";
359        printCondition(os, cond64);
360        os << suffix;
361    }
362    if (machInst.bigThumb)
363        os << ".w";
364    os << "   ";
365}
366
367void
368ArmStaticInst::printTarget(std::ostream &os, Addr target,
369                           const SymbolTable *symtab) const
370{
371    Addr symbolAddr;
372    std::string symbol;
373
374    if (symtab && symtab->findNearestSymbol(target, symbol, symbolAddr)) {
375        ccprintf(os, "<%s", symbol);
376        if (symbolAddr != target)
377            ccprintf(os, "+%d>", target - symbolAddr);
378        else
379            ccprintf(os, ">");
380    } else {
381        ccprintf(os, "%#x", target);
382    }
383}
384
385void
386ArmStaticInst::printCondition(std::ostream &os,
387                              unsigned code,
388                              bool noImplicit) const
389{
390    switch (code) {
391      case COND_EQ:
392        os << "eq";
393        break;
394      case COND_NE:
395        os << "ne";
396        break;
397      case COND_CS:
398        os << "cs";
399        break;
400      case COND_CC:
401        os << "cc";
402        break;
403      case COND_MI:
404        os << "mi";
405        break;
406      case COND_PL:
407        os << "pl";
408        break;
409      case COND_VS:
410        os << "vs";
411        break;
412      case COND_VC:
413        os << "vc";
414        break;
415      case COND_HI:
416        os << "hi";
417        break;
418      case COND_LS:
419        os << "ls";
420        break;
421      case COND_GE:
422        os << "ge";
423        break;
424      case COND_LT:
425        os << "lt";
426        break;
427      case COND_GT:
428        os << "gt";
429        break;
430      case COND_LE:
431        os << "le";
432        break;
433      case COND_AL:
434        // This one is implicit.
435        if (noImplicit)
436            os << "al";
437        break;
438      case COND_UC:
439        // Unconditional.
440        if (noImplicit)
441            os << "uc";
442        break;
443      default:
444        panic("Unrecognized condition code %d.\n", code);
445    }
446}
447
448void
449ArmStaticInst::printMemSymbol(std::ostream &os,
450                              const SymbolTable *symtab,
451                              const std::string &prefix,
452                              const Addr addr,
453                              const std::string &suffix) const
454{
455    Addr symbolAddr;
456    std::string symbol;
457    if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) {
458        ccprintf(os, "%s%s", prefix, symbol);
459        if (symbolAddr != addr)
460            ccprintf(os, "+%d", addr - symbolAddr);
461        ccprintf(os, suffix);
462    }
463}
464
465void
466ArmStaticInst::printShiftOperand(std::ostream &os,
467                                     IntRegIndex rm,
468                                     bool immShift,
469                                     uint32_t shiftAmt,
470                                     IntRegIndex rs,
471                                     ArmShiftType type) const
472{
473    bool firstOp = false;
474
475    if (rm != INTREG_ZERO) {
476        printIntReg(os, rm);
477    }
478
479    bool done = false;
480
481    if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
482        shiftAmt = 32;
483
484    switch (type) {
485      case LSL:
486        if (immShift && shiftAmt == 0) {
487            done = true;
488            break;
489        }
490        if (!firstOp)
491            os << ", ";
492        os << "LSL";
493        break;
494      case LSR:
495        if (!firstOp)
496            os << ", ";
497        os << "LSR";
498        break;
499      case ASR:
500        if (!firstOp)
501            os << ", ";
502        os << "ASR";
503        break;
504      case ROR:
505        if (immShift && shiftAmt == 0) {
506            if (!firstOp)
507                os << ", ";
508            os << "RRX";
509            done = true;
510            break;
511        }
512        if (!firstOp)
513            os << ", ";
514        os << "ROR";
515        break;
516      default:
517        panic("Tried to disassemble unrecognized shift type.\n");
518    }
519    if (!done) {
520        if (!firstOp)
521            os << " ";
522        if (immShift)
523            os << "#" << shiftAmt;
524        else
525            printIntReg(os, rs);
526    }
527}
528
529void
530ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
531                                  IntRegIndex rm, ArmExtendType type,
532                                  int64_t shiftAmt) const
533{
534    if (!firstOperand)
535        ccprintf(os, ", ");
536    printIntReg(os, rm);
537    if (type == UXTX && shiftAmt == 0)
538        return;
539    switch (type) {
540      case UXTB: ccprintf(os, ", UXTB");
541        break;
542      case UXTH: ccprintf(os, ", UXTH");
543        break;
544      case UXTW: ccprintf(os, ", UXTW");
545        break;
546      case UXTX: ccprintf(os, ", LSL");
547        break;
548      case SXTB: ccprintf(os, ", SXTB");
549        break;
550      case SXTH: ccprintf(os, ", SXTH");
551        break;
552      case SXTW: ccprintf(os, ", SXTW");
553        break;
554      case SXTX: ccprintf(os, ", SXTW");
555        break;
556    }
557    if (type == UXTX || shiftAmt)
558        ccprintf(os, " #%d", shiftAmt);
559}
560
561void
562ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
563        bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
564        IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
565        ArmShiftType type, uint64_t imm) const
566{
567    printMnemonic(os, s ? "s" : "");
568    bool firstOp = true;
569
570    // Destination
571    if (rd != INTREG_ZERO) {
572        firstOp = false;
573        printIntReg(os, rd);
574    }
575
576    // Source 1.
577    if (rn != INTREG_ZERO) {
578        if (!firstOp)
579            os << ", ";
580        firstOp = false;
581        printIntReg(os, rn);
582    }
583
584    if (!firstOp)
585        os << ", ";
586    if (withImm) {
587        ccprintf(os, "#%ld", imm);
588    } else {
589        printShiftOperand(os, rm, immShift, shiftAmt, rs, type);
590    }
591}
592
593std::string
594ArmStaticInst::generateDisassembly(Addr pc,
595                                   const SymbolTable *symtab) const
596{
597    std::stringstream ss;
598    printMnemonic(ss);
599    return ss.str();
600}
601
602
603Fault
604ArmStaticInst::advSIMDFPAccessTrap64(ExceptionLevel el) const
605{
606    switch (el) {
607      case EL1:
608        return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
609                                                EC_TRAPPED_SIMD_FP);
610      case EL2:
611        return std::make_shared<HypervisorTrap>(machInst, 0x1E00000,
612                                                EC_TRAPPED_SIMD_FP);
613      case EL3:
614        return std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000,
615                                                   EC_TRAPPED_SIMD_FP);
616
617      default:
618        panic("Illegal EL in advSIMDFPAccessTrap64\n");
619    }
620}
621
622
623Fault
624ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
625{
626    const ExceptionLevel el = (ExceptionLevel) (uint8_t)cpsr.el;
627
628    if (ArmSystem::haveVirtualization(tc) && el <= EL2) {
629        HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
630        if (cptrEnCheck.tfp)
631            return advSIMDFPAccessTrap64(EL2);
632    }
633
634    if (ArmSystem::haveSecurity(tc)) {
635        HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
636        if (cptrEnCheck.tfp)
637            return advSIMDFPAccessTrap64(EL3);
638    }
639
640    return NoFault;
641}
642
643Fault
644ArmStaticInst::checkFPAdvSIMDEnabled64(ThreadContext *tc,
645                                       CPSR cpsr, CPACR cpacr) const
646{
647    const ExceptionLevel el = (ExceptionLevel) (uint8_t)cpsr.el;
648    if ((el == EL0 && cpacr.fpen != 0x3) ||
649        (el == EL1 && !(cpacr.fpen & 0x1)))
650        return advSIMDFPAccessTrap64(EL1);
651
652    return checkFPAdvSIMDTrap64(tc, cpsr);
653}
654
655Fault
656ArmStaticInst::checkAdvSIMDOrFPEnabled32(ThreadContext *tc,
657                                         CPSR cpsr, CPACR cpacr,
658                                         NSACR nsacr, FPEXC fpexc,
659                                         bool fpexc_check, bool advsimd) const
660{
661    const bool have_virtualization = ArmSystem::haveVirtualization(tc);
662    const bool have_security = ArmSystem::haveSecurity(tc);
663    const bool is_secure = inSecureState(tc);
664    const ExceptionLevel cur_el = opModeToEL(currOpMode(tc));
665
666    if (cur_el == EL0 && ELIs64(tc, EL1))
667        return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);
668
669    uint8_t cpacr_cp10 = cpacr.cp10;
670    bool cpacr_asedis = cpacr.asedis;
671
672    if (have_security && !ELIs64(tc, EL3) && !is_secure) {
673        if (nsacr.nsasedis)
674            cpacr_asedis = true;
675        if (nsacr.cp10 == 0)
676            cpacr_cp10 = 0;
677    }
678
679    if (cur_el != EL2) {
680        if (advsimd && cpacr_asedis)
681            return disabledFault();
682
683        if ((cur_el == EL0 && cpacr_cp10 != 0x3) ||
684            (cur_el != EL0 && !(cpacr_cp10 & 0x1)))
685            return disabledFault();
686    }
687
688    if (fpexc_check && !fpexc.en)
689        return disabledFault();
690
691    // -- aarch32/exceptions/traps/AArch32.CheckFPAdvSIMDTrap --
692
693    if (have_virtualization && !is_secure && ELIs64(tc, EL2))
694        return checkFPAdvSIMDTrap64(tc, cpsr);
695
696    if (have_virtualization && !is_secure) {
697        HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
698        bool hcptr_cp10 = hcptr.tcp10;
699        bool hcptr_tase = hcptr.tase;
700
701        if (have_security && !ELIs64(tc, EL3) && !is_secure) {
702            if (nsacr.nsasedis)
703                hcptr_tase = true;
704            if (nsacr.cp10)
705                hcptr_cp10 = true;
706        }
707
708        if ((advsimd && hcptr_tase) || hcptr_cp10) {
709            const uint32_t iss = advsimd ? (1 << 5) : 0xA;
710            if (cur_el == EL2) {
711                return std::make_shared<UndefinedInstruction>(
712                    machInst, iss,
713                    EC_TRAPPED_HCPTR, mnemonic);
714            } else {
715                return std::make_shared<HypervisorTrap>(
716                    machInst, iss,
717                    EC_TRAPPED_HCPTR);
718            }
719
720        }
721    }
722
723    if (have_security && ELIs64(tc, EL3)) {
724        HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
725        if (cptrEnCheck.tfp)
726            return advSIMDFPAccessTrap64(EL3);
727    }
728
729    return NoFault;
730}
731
732
733static uint8_t
734getRestoredITBits(ThreadContext *tc, CPSR spsr)
735{
736    // See: shared/functions/system/RestoredITBits in the ARM ARM
737
738    const ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t)spsr.mode);
739    const uint8_t it = itState(spsr);
740
741    if (!spsr.t || spsr.il)
742        return 0;
743
744    // The IT bits are forced to zero when they are set to a reserved
745    // value.
746    if (bits(it, 7, 4) != 0 && bits(it, 3, 0) == 0)
747        return 0;
748
749    const bool itd = el == EL2 ?
750        ((SCTLR)tc->readMiscReg(MISCREG_HSCTLR)).itd :
751        ((SCTLR)tc->readMiscReg(MISCREG_SCTLR)).itd;
752
753    // The IT bits are forced to zero when returning to A32 state, or
754    // when returning to an EL with the ITD bit set to 1, and the IT
755    // bits are describing a multi-instruction block.
756    if (itd && bits(it, 2, 0) != 0)
757        return 0;
758
759    return it;
760}
761
762static bool
763illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
764{
765    const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
766    if (badMode(mode))
767        return true;
768
769    const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
770    const ExceptionLevel target_el = opModeToEL(mode);
771    if (target_el > opModeToEL(cur_mode))
772        return true;
773
774    if (target_el == EL3 && !ArmSystem::haveSecurity(tc))
775        return true;
776
777    if (target_el == EL2 && !ArmSystem::haveVirtualization(tc))
778        return true;
779
780    if (!spsr.width) {
781        // aarch64
782        if (!ArmSystem::highestELIs64(tc))
783            return true;
784
785        if (spsr & 0x2)
786            return true;
787        if (target_el == EL0 && spsr.sp)
788            return true;
789        if (target_el == EL2 && !((SCR)tc->readMiscReg(MISCREG_SCR_EL3)).ns)
790            return false;
791    } else {
792        return badMode32(mode);
793    }
794
795    return false;
796}
797
798CPSR
799ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
800{
801    CPSR new_cpsr = 0;
802
803    // gem5 doesn't implement single-stepping, so force the SS bit to
804    // 0.
805    new_cpsr.ss = 0;
806
807    if (illegalExceptionReturn(tc, cpsr, spsr)) {
808        new_cpsr.il = 1;
809    } else {
810        new_cpsr.il = spsr.il;
811        if (spsr.width && badMode32((OperatingMode)(uint8_t)spsr.mode)) {
812            new_cpsr.il = 1;
813        } else if (spsr.width) {
814            new_cpsr.mode = spsr.mode;
815        } else {
816            new_cpsr.el = spsr.el;
817            new_cpsr.sp = spsr.sp;
818        }
819    }
820
821    new_cpsr.nz = spsr.nz;
822    new_cpsr.c = spsr.c;
823    new_cpsr.v = spsr.v;
824    if (new_cpsr.width) {
825        // aarch32
826        const ITSTATE it = getRestoredITBits(tc, spsr);
827        new_cpsr.q = spsr.q;
828        new_cpsr.ge = spsr.ge;
829        new_cpsr.e = spsr.e;
830        new_cpsr.aif = spsr.aif;
831        new_cpsr.t = spsr.t;
832        new_cpsr.it2 = it.top6;
833        new_cpsr.it1 = it.bottom2;
834    } else {
835        // aarch64
836        new_cpsr.daif = spsr.daif;
837    }
838
839    return new_cpsr;
840}
841
842
843
844}
845