pseudo.hh revision 10696:b5e5068fcb26 
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Sandberg
41 *          Stephen Hines
42 */
43
44#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
45#define __ARCH_ARM_INSTS_PSEUDO_HH__
46
47#include "arch/arm/insts/static_inst.hh"
48
49class DecoderFaultInst : public ArmStaticInst
50{
51  protected:
52    DecoderFault faultId;
53
54    const char *faultName() const;
55
56  public:
57    DecoderFaultInst(ExtMachInst _machInst);
58
59    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
60
61    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
62};
63
64/**
65 * Static instruction class for unimplemented instructions that
66 * cause simulator termination.  Note that these are recognized
67 * (legal) instructions that the simulator does not support; the
68 * 'Unknown' class is used for unrecognized/illegal instructions.
69 * This is a leaf class.
70 */
71class FailUnimplemented : public ArmStaticInst
72{
73  private:
74    /// Full mnemonic for MRC and MCR instructions including the
75    /// coproc. register name
76    std::string fullMnemonic;
77
78  public:
79    FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
80    FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
81                      const std::string& _fullMnemonic);
82
83    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
84
85    std::string
86    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
87};
88
89/**
90 * Base class for unimplemented instructions that cause a warning
91 * to be printed (but do not terminate simulation).  This
92 * implementation is a little screwy in that it will print a
93 * warning for each instance of a particular unimplemented machine
94 * instruction, not just for each unimplemented opcode.  Should
95 * probably make the 'warned' flag a static member of the derived
96 * class.
97 */
98class WarnUnimplemented : public ArmStaticInst
99{
100  private:
101    /// Have we warned on this instruction yet?
102    mutable bool warned;
103    /// Full mnemonic for MRC and MCR instructions including the
104    /// coproc. register name
105    std::string fullMnemonic;
106
107  public:
108    WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
109    WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
110                      const std::string& _fullMnemonic);
111
112    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
113
114    std::string
115    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
116};
117
118class FlushPipeInst : public ArmStaticInst
119{
120  public:
121    FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst);
122
123    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
124
125    std::string
126    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
127
128};
129
130
131#endif
132