pseudo.hh revision 10696:b5e5068fcb26
11758SN/A/*
21762SN/A * Copyright (c) 2014 ARM Limited
31758SN/A * All rights reserved
41758SN/A *
51758SN/A * The license below extends only to copyright in the software and shall
61758SN/A * not be construed as granting a license to any other intellectual
71758SN/A * property including but not limited to intellectual property relating
81758SN/A * to a hardware implementation of the functionality of the software
91758SN/A * licensed hereunder.  You may use the software subject to the license
101758SN/A * terms below provided that you ensure that this notice is replicated
111758SN/A * unmodified and in its entirety in all distributions of the software,
121758SN/A * modified or unmodified, in source code or in binary form.
131758SN/A *
141758SN/A * Copyright (c) 2007-2008 The Florida State University
151758SN/A * All rights reserved.
161758SN/A *
171758SN/A * Redistribution and use in source and binary forms, with or without
181758SN/A * modification, are permitted provided that the following conditions are
191758SN/A * met: redistributions of source code must retain the above copyright
201758SN/A * notice, this list of conditions and the following disclaimer;
211758SN/A * redistributions in binary form must reproduce the above copyright
221758SN/A * notice, this list of conditions and the following disclaimer in the
231758SN/A * documentation and/or other materials provided with the distribution;
241758SN/A * neither the name of the copyright holders nor the names of its
251758SN/A * contributors may be used to endorse or promote products derived from
261758SN/A * this software without specific prior written permission.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311758SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
331147SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341147SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
361858SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372107SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
381858SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
391147SN/A *
40924SN/A * Authors: Andreas Sandberg
412107SN/A *          Stephen Hines
422107SN/A */
432107SN/A
441858SN/A#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
451147SN/A#define __ARCH_ARM_INSTS_PSEUDO_HH__
46924SN/A
471147SN/A#include "arch/arm/insts/static_inst.hh"
48924SN/A
49924SN/Aclass DecoderFaultInst : public ArmStaticInst
501147SN/A{
511147SN/A  protected:
521147SN/A    DecoderFault faultId;
531147SN/A
541147SN/A    const char *faultName() const;
551147SN/A
561147SN/A  public:
571147SN/A    DecoderFaultInst(ExtMachInst _machInst);
58924SN/A
591858SN/A    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
601147SN/A
611147SN/A    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
62924SN/A};
631147SN/A
641147SN/A/**
65924SN/A * Static instruction class for unimplemented instructions that
661147SN/A * cause simulator termination.  Note that these are recognized
671147SN/A * (legal) instructions that the simulator does not support; the
681147SN/A * 'Unknown' class is used for unrecognized/illegal instructions.
691147SN/A * This is a leaf class.
701147SN/A */
711805SN/Aclass FailUnimplemented : public ArmStaticInst
721805SN/A{
731858SN/A  private:
741805SN/A    /// Full mnemonic for MRC and MCR instructions including the
751805SN/A    /// coproc. register name
761805SN/A    std::string fullMnemonic;
771805SN/A
781805SN/A  public:
791805SN/A    FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
801805SN/A    FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
81924SN/A                      const std::string& _fullMnemonic);
821147SN/A
831147SN/A    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
841147SN/A
851147SN/A    std::string
861147SN/A    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
871147SN/A};
881147SN/A
891147SN/A/**
901147SN/A * Base class for unimplemented instructions that cause a warning
912SN/A * to be printed (but do not terminate simulation).  This
921147SN/A * implementation is a little screwy in that it will print a
931147SN/A * warning for each instance of a particular unimplemented machine
941147SN/A * instruction, not just for each unimplemented opcode.  Should
951147SN/A * probably make the 'warned' flag a static member of the derived
961147SN/A * class.
971147SN/A */
981147SN/Aclass WarnUnimplemented : public ArmStaticInst
991147SN/A{
1002SN/A  private:
1011147SN/A    /// Have we warned on this instruction yet?
1022SN/A    mutable bool warned;
1031147SN/A    /// Full mnemonic for MRC and MCR instructions including the
1041147SN/A    /// coproc. register name
1051147SN/A    std::string fullMnemonic;
1062SN/A
1071147SN/A  public:
1081147SN/A    WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
1091147SN/A    WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
1102SN/A                      const std::string& _fullMnemonic);
1111147SN/A
1121147SN/A    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
1131147SN/A
1141147SN/A    std::string
1151147SN/A    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1161147SN/A};
1171147SN/A
1181147SN/Aclass FlushPipeInst : public ArmStaticInst
1192SN/A{
1201147SN/A  public:
1211147SN/A    FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst);
1222SN/A
1231147SN/A    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
1242SN/A
1251147SN/A    std::string
126    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
127
128};
129
130
131#endif
132