pseudo.cc revision 12763:37c243ed1112 
1/*
2 * Copyright (c) 2014,2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Sandberg
41 *          Stephen Hines
42 */
43
44#include "arch/arm/insts/pseudo.hh"
45
46#include "cpu/exec_context.hh"
47
48DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
49    : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
50      faultId(static_cast<DecoderFault>(
51                  static_cast<uint8_t>(_machInst.decoderFault)))
52{
53    // Don't call execute() if we're on a speculative path and the
54    // fault is an internal panic fault.
55    flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC);
56}
57
58Fault
59DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
60{
61    const PCState pc_state(xc->pcState());
62    const Addr pc(pc_state.instAddr());
63
64    switch (faultId) {
65      case DecoderFault::UNALIGNED:
66        if (machInst.aarch64) {
67            return std::make_shared<PCAlignmentFault>(pc);
68        } else {
69            // TODO: We should check if we the receiving end is in
70            // aarch64 mode and raise a PCAlignment fault instead.
71            return std::make_shared<PrefetchAbort>(
72                pc, ArmFault::AlignmentFault);
73        }
74
75      case DecoderFault::PANIC:
76        panic("Internal error in instruction decoder\n");
77
78      case DecoderFault::OK:
79        panic("Decoder fault instruction without decoder fault.\n");
80    }
81
82    panic("Unhandled fault type");
83}
84
85const char *
86DecoderFaultInst::faultName() const
87{
88    switch (faultId) {
89      case DecoderFault::OK:
90        return "OK";
91
92      case DecoderFault::UNALIGNED:
93        return "UnalignedInstruction";
94
95      case DecoderFault::PANIC:
96        return "DecoderPanic";
97    }
98
99    panic("Unhandled fault type");
100}
101
102std::string
103DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
104{
105    return csprintf("gem5fault %s", faultName());
106}
107
108
109
110FailUnimplemented::FailUnimplemented(const char *_mnemonic,
111                                     ExtMachInst _machInst)
112    : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
113{
114    // don't call execute() (which panics) if we're on a
115    // speculative path
116    flags[IsNonSpeculative] = true;
117}
118
119FailUnimplemented::FailUnimplemented(const char *_mnemonic,
120                                     ExtMachInst _machInst,
121                                     const std::string& _fullMnemonic)
122    : ArmStaticInst(_mnemonic, _machInst, No_OpClass),
123      fullMnemonic(_fullMnemonic)
124{
125    // don't call execute() (which panics) if we're on a
126    // speculative path
127    flags[IsNonSpeculative] = true;
128}
129
130Fault
131FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
132{
133    return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
134}
135
136std::string
137FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
138{
139    return csprintf("%-10s (unimplemented)",
140                    fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
141}
142
143
144
145WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
146                                     ExtMachInst _machInst)
147    : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
148{
149    // don't call execute() (which panics) if we're on a
150    // speculative path
151    flags[IsNonSpeculative] = true;
152}
153
154WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
155                                     ExtMachInst _machInst,
156                                     const std::string& _fullMnemonic)
157    : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
158      fullMnemonic(_fullMnemonic)
159{
160    // don't call execute() (which panics) if we're on a
161    // speculative path
162    flags[IsNonSpeculative] = true;
163}
164
165Fault
166WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
167{
168    if (!warned) {
169        warn("\tinstruction '%s' unimplemented\n",
170             fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
171        warned = true;
172    }
173
174    return NoFault;
175}
176
177std::string
178WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
179{
180    return csprintf("%-10s (unimplemented)",
181                    fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
182}
183
184McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
185                               uint64_t _iss, MiscRegIndex _miscReg)
186    : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
187{
188    flags[IsNonSpeculative] = true;
189    iss = _iss;
190    miscReg = _miscReg;
191}
192
193Fault
194McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
195{
196    uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
197    uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
198    uint32_t scr = xc->readMiscReg(MISCREG_SCR);
199    uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
200    uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
201    uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
202
203    bool hypTrap  = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
204                                      hcptr, iss);
205    if (hypTrap) {
206        return std::make_shared<HypervisorTrap>(machInst, iss,
207                                                EC_TRAPPED_CP15_MCR_MRC);
208    } else {
209        return NoFault;
210    }
211}
212
213std::string
214McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
215{
216    return csprintf("%-10s (pipe flush)", mnemonic);
217}
218
219McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic,
220                                     ExtMachInst _machInst, uint64_t _iss,
221                                     MiscRegIndex _miscReg)
222    : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg)
223{}
224
225Fault
226McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
227{
228    uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
229    uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
230    uint32_t scr = xc->readMiscReg(MISCREG_SCR);
231    uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
232    uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
233    uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
234
235    bool hypTrap  = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
236                                      hcptr, iss);
237    if (hypTrap) {
238        return std::make_shared<HypervisorTrap>(machInst, iss,
239                                                EC_TRAPPED_CP15_MCR_MRC);
240    } else {
241        return std::make_shared<UndefinedInstruction>(machInst, false,
242                                                      mnemonic);
243    }
244}
245
246std::string
247McrMrcImplDefined::generateDisassembly(Addr pc,
248                                       const SymbolTable *symtab) const
249{
250    return csprintf("%-10s (implementation defined)", mnemonic);
251}
252
253IllegalExecInst::IllegalExecInst(ExtMachInst _machInst)
254    : ArmStaticInst("Illegal Execution", _machInst, No_OpClass)
255{}
256
257Fault
258IllegalExecInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
259{
260    return std::make_shared<IllegalInstSetStateFault>();
261}
262