misc64.hh revision 14127:65faf17eea53 
1/*
2 * Copyright (c) 2011-2013,2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Giacomo Travaglini
39 */
40
41#ifndef __ARCH_ARM_INSTS_MISC64_HH__
42#define __ARCH_ARM_INSTS_MISC64_HH__
43
44#include "arch/arm/insts/static_inst.hh"
45
46class ImmOp64 : public ArmStaticInst
47{
48  protected:
49    uint64_t imm;
50
51    ImmOp64(const char *mnem, ExtMachInst _machInst,
52            OpClass __opClass, uint64_t _imm) :
53        ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
54    {}
55
56    std::string generateDisassembly(
57            Addr pc, const SymbolTable *symtab) const override;
58};
59
60class RegRegImmImmOp64 : public ArmStaticInst
61{
62  protected:
63    IntRegIndex dest;
64    IntRegIndex op1;
65    uint64_t imm1;
66    uint64_t imm2;
67
68    RegRegImmImmOp64(const char *mnem, ExtMachInst _machInst,
69                     OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
70                     uint64_t _imm1, uint64_t _imm2) :
71        ArmStaticInst(mnem, _machInst, __opClass),
72        dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
73    {}
74
75    std::string generateDisassembly(
76            Addr pc, const SymbolTable *symtab) const override;
77};
78
79class RegRegRegImmOp64 : public ArmStaticInst
80{
81  protected:
82    IntRegIndex dest;
83    IntRegIndex op1;
84    IntRegIndex op2;
85    uint64_t imm;
86
87    RegRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
88                     OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
89                     IntRegIndex _op2, uint64_t _imm) :
90        ArmStaticInst(mnem, _machInst, __opClass),
91        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
92    {}
93
94    std::string generateDisassembly(
95            Addr pc, const SymbolTable *symtab) const override;
96};
97
98class UnknownOp64 : public ArmStaticInst
99{
100  protected:
101
102    UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
103        ArmStaticInst(mnem, _machInst, __opClass)
104    {}
105
106    std::string generateDisassembly(
107            Addr pc, const SymbolTable *symtab) const override;
108};
109
110/**
111 * This class is implementing the Base class for a generic AArch64
112 * instruction which is making use of system registers (MiscReg), like
113 * MSR,MRS,SYS.  The common denominator or those instruction is the
114 * chance that the system register access is trapped to an upper
115 * Exception level. MiscRegOp64 is providing that feature.  Other
116 * "pseudo" instructions, like access to implementation defined
117 * registers can inherit from this class to make use of the trapping
118 * functionalities even if there is no data movement between GPRs and
119 * system register.
120 */
121class MiscRegOp64 : public ArmStaticInst
122{
123  protected:
124    bool miscRead;
125
126    MiscRegOp64(const char *mnem, ExtMachInst _machInst,
127                OpClass __opClass, bool misc_read) :
128        ArmStaticInst(mnem, _machInst, __opClass),
129        miscRead(misc_read)
130    {}
131
132    Fault trap(ThreadContext *tc, MiscRegIndex misc_reg,
133               ExceptionLevel el, uint32_t immediate) const;
134  private:
135    bool checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
136                      ExceptionLevel el) const;
137
138    bool checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
139                      ExceptionLevel el, bool *is_vfp_neon) const;
140
141    bool checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
142                      ExceptionLevel el, bool *is_vfp_neon) const;
143
144};
145
146class MiscRegImmOp64 : public MiscRegOp64
147{
148  protected:
149    MiscRegIndex dest;
150    uint32_t imm;
151
152    MiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
153                   OpClass __opClass, MiscRegIndex _dest,
154                   uint32_t _imm) :
155        MiscRegOp64(mnem, _machInst, __opClass, false),
156        dest(_dest), imm(_imm)
157    {}
158
159    /** Returns the "register view" of the immediate field.
160     * as if it was a MSR PSTATE REG instruction.
161     * This means basically shifting and masking depending on
162     * which PSTATE field is being set/cleared.
163     */
164    RegVal miscRegImm() const;
165
166    std::string generateDisassembly(
167            Addr pc, const SymbolTable *symtab) const override;
168};
169
170class MiscRegRegImmOp64 : public MiscRegOp64
171{
172  protected:
173    MiscRegIndex dest;
174    IntRegIndex op1;
175    uint32_t imm;
176
177    MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
178                      OpClass __opClass, MiscRegIndex _dest,
179                      IntRegIndex _op1, uint32_t _imm) :
180        MiscRegOp64(mnem, _machInst, __opClass, false),
181        dest(_dest), op1(_op1), imm(_imm)
182    {}
183
184    std::string generateDisassembly(
185            Addr pc, const SymbolTable *symtab) const override;
186};
187
188class RegMiscRegImmOp64 : public MiscRegOp64
189{
190  protected:
191    IntRegIndex dest;
192    MiscRegIndex op1;
193    uint32_t imm;
194
195    RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
196                      OpClass __opClass, IntRegIndex _dest,
197                      MiscRegIndex _op1, uint32_t _imm) :
198        MiscRegOp64(mnem, _machInst, __opClass, true),
199        dest(_dest), op1(_op1), imm(_imm)
200    {}
201
202    std::string generateDisassembly(
203            Addr pc, const SymbolTable *symtab) const override;
204};
205
206class MiscRegImplDefined64 : public MiscRegOp64
207{
208  protected:
209    const std::string fullMnemonic;
210    const MiscRegIndex miscReg;
211    const uint32_t imm;
212    const bool warning;
213
214  public:
215    MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst,
216                         MiscRegIndex misc_reg, bool misc_read,
217                         uint32_t _imm, const std::string full_mnem,
218                         bool _warning) :
219        MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
220        fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
221        warning(_warning)
222    {
223        assert(miscReg == MISCREG_IMPDEF_UNIMPL);
224    }
225
226  protected:
227    Fault execute(ExecContext *xc,
228                  Trace::InstRecord *traceData) const override;
229
230    std::string generateDisassembly(
231            Addr pc, const SymbolTable *symtab) const override;
232};
233
234#endif
235