misc64.hh revision 12616:4b463b4dc098
1/* 2 * Copyright (c) 2011-2013,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_ARM_INSTS_MISC64_HH__ 41#define __ARCH_ARM_INSTS_MISC64_HH__ 42 43#include "arch/arm/insts/static_inst.hh" 44 45class ImmOp64 : public ArmStaticInst 46{ 47 protected: 48 uint64_t imm; 49 50 ImmOp64(const char *mnem, ExtMachInst _machInst, 51 OpClass __opClass, uint64_t _imm) : 52 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm) 53 {} 54 55 std::string generateDisassembly( 56 Addr pc, const SymbolTable *symtab) const override; 57}; 58 59class RegRegImmImmOp64 : public ArmStaticInst 60{ 61 protected: 62 IntRegIndex dest; 63 IntRegIndex op1; 64 uint64_t imm1; 65 uint64_t imm2; 66 67 RegRegImmImmOp64(const char *mnem, ExtMachInst _machInst, 68 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 69 uint64_t _imm1, uint64_t _imm2) : 70 ArmStaticInst(mnem, _machInst, __opClass), 71 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 72 {} 73 74 std::string generateDisassembly( 75 Addr pc, const SymbolTable *symtab) const override; 76}; 77 78class RegRegRegImmOp64 : public ArmStaticInst 79{ 80 protected: 81 IntRegIndex dest; 82 IntRegIndex op1; 83 IntRegIndex op2; 84 uint64_t imm; 85 86 RegRegRegImmOp64(const char *mnem, ExtMachInst _machInst, 87 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 88 IntRegIndex _op2, uint64_t _imm) : 89 ArmStaticInst(mnem, _machInst, __opClass), 90 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 91 {} 92 93 std::string generateDisassembly( 94 Addr pc, const SymbolTable *symtab) const override; 95}; 96 97class UnknownOp64 : public ArmStaticInst 98{ 99 protected: 100 101 UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 102 ArmStaticInst(mnem, _machInst, __opClass) 103 {} 104 105 std::string generateDisassembly( 106 Addr pc, const SymbolTable *symtab) const override; 107}; 108 109class MiscRegRegImmOp64 : public ArmStaticInst 110{ 111 protected: 112 MiscRegIndex dest; 113 IntRegIndex op1; 114 uint32_t imm; 115 116 MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst, 117 OpClass __opClass, MiscRegIndex _dest, 118 IntRegIndex _op1, uint32_t _imm) : 119 ArmStaticInst(mnem, _machInst, __opClass), 120 dest(_dest), op1(_op1), imm(_imm) 121 {} 122 123 std::string generateDisassembly( 124 Addr pc, const SymbolTable *symtab) const override; 125}; 126 127class RegMiscRegImmOp64 : public ArmStaticInst 128{ 129 protected: 130 IntRegIndex dest; 131 MiscRegIndex op1; 132 uint32_t imm; 133 134 RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst, 135 OpClass __opClass, IntRegIndex _dest, 136 MiscRegIndex _op1, uint32_t _imm) : 137 ArmStaticInst(mnem, _machInst, __opClass), 138 dest(_dest), op1(_op1), imm(_imm) 139 {} 140 141 std::string generateDisassembly( 142 Addr pc, const SymbolTable *symtab) const override; 143}; 144 145#endif 146