misc.hh revision 7409:1ff897327905
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_ARM_INSTS_MISC_HH__ 41#define __ARCH_ARM_INSTS_MISC_HH__ 42 43#include "arch/arm/insts/pred_inst.hh" 44 45class MrsOp : public PredOp 46{ 47 protected: 48 IntRegIndex dest; 49 50 MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 51 IntRegIndex _dest) : 52 PredOp(mnem, _machInst, __opClass), dest(_dest) 53 {} 54 55 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 56}; 57 58class MsrBase : public PredOp 59{ 60 protected: 61 uint8_t byteMask; 62 63 MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 64 uint8_t _byteMask) : 65 PredOp(mnem, _machInst, __opClass), byteMask(_byteMask) 66 {} 67 68 void printMsrBase(std::ostream &os) const; 69}; 70 71class MsrImmOp : public MsrBase 72{ 73 protected: 74 uint32_t imm; 75 76 MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 77 uint32_t _imm, uint8_t _byteMask) : 78 MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm) 79 {} 80 81 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 82}; 83 84class MsrRegOp : public MsrBase 85{ 86 protected: 87 IntRegIndex op1; 88 89 MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 90 IntRegIndex _op1, uint8_t _byteMask) : 91 MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1) 92 {} 93 94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 95}; 96 97class ImmOp : public PredOp 98{ 99 protected: 100 uint64_t imm; 101 102 ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 103 uint64_t _imm) : 104 PredOp(mnem, _machInst, __opClass), imm(_imm) 105 {} 106 107 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 108}; 109 110class RegImmOp : public PredOp 111{ 112 protected: 113 IntRegIndex dest; 114 uint64_t imm; 115 116 RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 117 IntRegIndex _dest, uint64_t _imm) : 118 PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm) 119 {} 120 121 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 122}; 123 124class RegRegOp : public PredOp 125{ 126 protected: 127 IntRegIndex dest; 128 IntRegIndex op1; 129 130 RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 131 IntRegIndex _dest, IntRegIndex _op1) : 132 PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1) 133 {} 134 135 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 136}; 137 138class RegImmRegOp : public PredOp 139{ 140 protected: 141 IntRegIndex dest; 142 uint64_t imm; 143 IntRegIndex op1; 144 145 RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 146 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) : 147 PredOp(mnem, _machInst, __opClass), 148 dest(_dest), imm(_imm), op1(_op1) 149 {} 150 151 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 152}; 153 154class RegRegRegImmOp : public PredOp 155{ 156 protected: 157 IntRegIndex dest; 158 IntRegIndex op1; 159 IntRegIndex op2; 160 uint64_t imm; 161 162 RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 163 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 164 uint64_t _imm) : 165 PredOp(mnem, _machInst, __opClass), 166 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 167 {} 168 169 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 170}; 171 172class RegRegRegRegOp : public PredOp 173{ 174 protected: 175 IntRegIndex dest; 176 IntRegIndex op1; 177 IntRegIndex op2; 178 IntRegIndex op3; 179 180 RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 181 IntRegIndex _dest, IntRegIndex _op1, 182 IntRegIndex _op2, IntRegIndex _op3) : 183 PredOp(mnem, _machInst, __opClass), 184 dest(_dest), op1(_op1), op2(_op2), op3(_op3) 185 {} 186 187 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 188}; 189 190class RegRegRegOp : public PredOp 191{ 192 protected: 193 IntRegIndex dest; 194 IntRegIndex op1; 195 IntRegIndex op2; 196 197 RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 198 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 199 PredOp(mnem, _machInst, __opClass), 200 dest(_dest), op1(_op1), op2(_op2) 201 {} 202 203 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 204}; 205 206class RegRegImmOp : public PredOp 207{ 208 protected: 209 IntRegIndex dest; 210 IntRegIndex op1; 211 uint64_t imm; 212 213 RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 214 IntRegIndex _dest, IntRegIndex _op1, 215 uint64_t _imm) : 216 PredOp(mnem, _machInst, __opClass), 217 dest(_dest), op1(_op1), imm(_imm) 218 {} 219 220 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 221}; 222 223class RegRegImmImmOp : public PredOp 224{ 225 protected: 226 IntRegIndex dest; 227 IntRegIndex op1; 228 uint64_t imm1; 229 uint64_t imm2; 230 231 RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 232 IntRegIndex _dest, IntRegIndex _op1, 233 uint64_t _imm1, uint64_t _imm2) : 234 PredOp(mnem, _machInst, __opClass), 235 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 236 {} 237 238 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 239}; 240 241class RegImmRegShiftOp : public PredOp 242{ 243 protected: 244 IntRegIndex dest; 245 uint64_t imm; 246 IntRegIndex op1; 247 int32_t shiftAmt; 248 ArmShiftType shiftType; 249 250 RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 251 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, 252 int32_t _shiftAmt, ArmShiftType _shiftType) : 253 PredOp(mnem, _machInst, __opClass), 254 dest(_dest), imm(_imm), op1(_op1), 255 shiftAmt(_shiftAmt), shiftType(_shiftType) 256 {} 257 258 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 259}; 260 261class UnknownOp : public PredOp 262{ 263 protected: 264 265 UnknownOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 266 PredOp(mnem, _machInst, __opClass) 267 {} 268 269 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 270}; 271 272#endif 273